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/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dplatform.mk11 include plat/st/common/common.mk
109 STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S
110 STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S
116 STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
196 PLAT_INCLUDES += -Iplat/st/stm32mp2/include/
197 PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/
198 PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/
201 PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
202 PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
204 PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/constraints/
H A Dmt_spm_rc_cpu_buck_ldo.c66 const struct rc_common_state *st = (const struct rc_common_state *)val; in update_rc_status() local
68 if (st == NULL) { in update_rc_status()
72 if ((st->type == CONSTRAINT_UPDATE_VALID) && st->value) { in update_rc_status()
73 if ((st->id == MT_RM_CONSTRAINT_ID_ALL) || in update_rc_status()
74 (st->id == MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO)) { in update_rc_status()
75 struct constraint_status *con = (struct constraint_status *)st->value; in update_rc_status()
77 if ((st->act & MT_LPM_SMC_ACT_CLR) > 0U) { in update_rc_status()
157 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_cpu_buck_ldo() local
159 if (st == NULL) { in spm_get_status_rc_cpu_buck_ldo()
163 if ((st->id == MT_RM_CONSTRAINT_ID_ALL) || in spm_get_status_rc_cpu_buck_ldo()
[all …]
H A Dmt_spm_rc_dram.c159 const struct rc_common_state *st; in update_rc_status() local
161 st = (const struct rc_common_state *)val; in update_rc_status()
163 if (st == NULL) { in update_rc_status()
167 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in update_rc_status()
170 spm_rc_condition_modifier(st->id, st->act, st->value, in update_rc_status()
172 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in update_rc_status()
173 (st->type == CONSTRAINT_RESIDNECY)) { in update_rc_status()
174 spm_rc_constraint_status_set(st->id, st->type, st->act, in update_rc_status()
176 (struct constraint_status * const)st->value, in update_rc_status()
179 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); in update_rc_status()
[all …]
H A Dmt_spm_rc_syspll.c202 const struct rc_common_state *st; in update_rc_status() local
204 st = (const struct rc_common_state *)val; in update_rc_status()
206 if (st == NULL) { in update_rc_status()
210 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in update_rc_status()
213 spm_rc_condition_modifier(st->id, st->act, st->value, in update_rc_status()
215 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in update_rc_status()
216 (st->type == CONSTRAINT_RESIDNECY)) { in update_rc_status()
217 spm_rc_constraint_status_set(st->id, st->type, st->act, in update_rc_status()
219 (struct constraint_status * const)st->value, in update_rc_status()
222 INFO("[%s:%d] - Unknown type: 0x%x\n", __func__, __LINE__, st->type); in update_rc_status()
[all …]
/rk3399_ARM-atf/fdts/
H A Dstm32mp157c-ed1.dts4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
36 st,non-secure-otp;
41 st,digbypass;
75 compatible = "st,stpmic1";
83 compatible = "st,stpmic1-regulators";
115 st,mask-reset;
145 st,regulator-sink-source;
199 st,clksrc = <
213 st,clkdiv = <
[all …]
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi4 * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
34 st,busclk = <
43 st,flexgen = <
57 st,kerclk = <
62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200Mhz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_600Mhz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200Mhz>;
[all …]
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi4 * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
34 st,busclk = <
43 st,flexgen = <
57 st,kerclk = <
62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200Mhz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_600Mhz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200Mhz>;
[all …]
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi29 st,busclk = <
38 st,flexgen = <
52 st,kerclk = <
57 pll1: st,pll-1 {
58 st,pll = <&pll1_cfg_1200Mhz>;
66 pll2: st,pll-2 {
67 st,pll = <&pll2_cfg_600Mhz>;
75 pll4: st,pll-4 {
76 st,pll = <&pll4_cfg_1200Mhz>;
84 pll5: st,pll-5 {
[all …]
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi33 st,busclk = <
42 st,flexgen = <
55 st,kerclk = <
60 pll1: st,pll-1 {
61 st,pll = <&pll1_cfg_1200Mhz>;
69 pll2: st,pll-2 {
70 st,pll = <&pll2_cfg_600Mhz>;
78 pll4: st,pll-4 {
79 st,pll = <&pll4_cfg_1200Mhz>;
87 pll5: st,pll-5 {
[all …]
H A Dstm32mp157a-avenger96.dts22 compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
53 compatible = "st,stpmic1";
60 st,main-control-register = <0x04>;
61 st,vin-control-register = <0xc0>;
62 st,usb-control-register = <0x30>;
65 compatible = "st,stpmic1-regulators";
97 st,mask-reset;
127 st,regulator-sink-source;
181 st,clksrc = <
225 st,clkdiv = <
[all …]
H A Dstm32mp15xx-osd32.dtsi24 compatible = "st,stpmic1";
31 compatible = "st,stpmic1-regulators";
60 st,mask-reset;
92 st,regulator-sink-source;
136 compatible = "st,stpmic1-wdt";
168 st,non-secure-otp;
173 st,digbypass;
190 st,clksrc = <
234 st,clkdiv = <
248 st,pll_vco {
[all …]
H A Dstm32mp15xx-dkx.dtsi4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
34 st,non-secure-otp;
39 st,digbypass;
69 compatible = "st,stpmic1";
77 compatible = "st,stpmic1-regulators";
116 st,mask-reset;
148 st,regulator-sink-source;
203 st,clksrc = <
215 st,clkdiv = <
227 st,pll_vco {
[all …]
H A Dstm32mp135f-dk.dts4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
17 compatible = "st,stm32mp135f-dk", "st,stm32mp135";
55 st,non-secure-otp;
81 compatible = "st,stpmic1";
87 compatible = "st,stpmic1-regulators";
121 st,mask-reset;
191 st,clksrc = <
208 st,clkdiv = <
219 st,pll_vco {
239 pll2:st,pll@1 {
[all …]
H A Dstm32mp151.dtsi4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
82 compatible = "st,stm32-timers";
90 compatible = "st,stm32h7-uart";
99 compatible = "st,stm32h7-uart";
108 compatible = "st,stm32h7-uart";
118 compatible = "st,stm32h7-uart";
127 compatible = "st,stm32mp15-i2c";
136 st,syscfg-fmp = <&syscfg 0x4 0x2>;
142 compatible = "st,stm32h7-uart";
151 compatible = "st,stm32h7-uart";
[all …]
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi4 * Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
34 st,busclk = <
44 st,flexgen = <
57 st,kerclk = <
62 pll1: st,pll-1 {
63 st,pll = <&pll1_cfg_1200MHz>;
71 pll2: st,pll-2 {
72 st,pll = <&pll2_cfg_400MHz>;
80 pll4: st,pll-4 {
81 st,pll = <&pll4_cfg_1200MHz>;
H A Dstm32mp251.dtsi4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
88 compatible = "st,stm32mp25-rifsc";
94 compatible = "st,stm32h7-uart";
102 compatible = "st,stm32h7-uart";
110 compatible = "st,stm32h7-uart";
118 compatible = "st,stm32h7-uart";
126 compatible = "st,stm32mp25-i2c";
134 compatible = "st,stm32mp25-i2c";
142 compatible = "st,stm32mp25-i2c";
150 compatible = "st,stm32mp25-i2c";
[all …]
H A Dstm32mp15-ddr.dtsi7 st,mem-name = DDR_MEM_NAME;
8 st,mem-speed = <DDR_MEM_SPEED>;
9 st,mem-size = <DDR_MEM_SIZE>;
11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
86 st,phy-reg = <
100 st,phy-timing = <
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/
H A Dmt_spm_rc_vcore.c141 const struct rc_common_state *st = (const struct rc_common_state *)val; in spm_update_rc_vcore() local
144 if (!st) in spm_update_rc_vcore()
146 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in spm_update_rc_vcore()
150 st->id, st->act, st->value, in spm_update_rc_vcore()
152 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_vcore()
153 (st->type == CONSTRAINT_RESIDNECY)) in spm_update_rc_vcore()
155 st->id, st->type, st->act, in spm_update_rc_vcore()
158 st->value, in spm_update_rc_vcore()
163 __LINE__, st->type); in spm_update_rc_vcore()
264 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_vcore() local
[all …]
H A Dmt_spm_rc_bus26m.c144 const struct rc_common_state *st; in spm_update_rc_bus26m() local
146 st = (const struct rc_common_state *)val; in spm_update_rc_bus26m()
148 if (!st) in spm_update_rc_bus26m()
150 if (st->type == CONSTRAINT_UPDATE_COND_CHECK) { in spm_update_rc_bus26m()
153 spm_rc_condition_modifier(st->id, st->act, st->value, in spm_update_rc_bus26m()
156 } else if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_bus26m()
157 (st->type == CONSTRAINT_RESIDNECY)) { in spm_update_rc_bus26m()
158 spm_rc_constraint_status_set(st->id, st->type, st->act, in spm_update_rc_bus26m()
160 st->value, &status); in spm_update_rc_bus26m()
163 __LINE__, st->type); in spm_update_rc_bus26m()
[all …]
H A Dmt_spm_rc_syspll.c111 const struct rc_common_state *st; in spm_update_rc_syspll() local
113 st = (const struct rc_common_state *)val; in spm_update_rc_syspll()
115 if (!st) in spm_update_rc_syspll()
117 if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_syspll()
118 (st->type == CONSTRAINT_RESIDNECY)) in spm_update_rc_syspll()
119 spm_rc_constraint_status_set(st->id, st->type, st->act, in spm_update_rc_syspll()
121 st->value, &status); in spm_update_rc_syspll()
124 __LINE__, st->type); in spm_update_rc_syspll()
237 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_syspll() local
239 if (!st) in spm_get_status_rc_syspll()
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/sp_min/
H A Dsp_min-stm32mp1.mk19 BL32_SOURCES += drivers/st/etzpc/etzpc.c \
21 plat/st/stm32mp1/sp_min/sp_min_setup.c \
22 plat/st/stm32mp1/stm32mp1_pm.c \
23 plat/st/stm32mp1/stm32mp1_shared_resources.c \
24 plat/st/stm32mp1/stm32mp1_topology.c
35 plat/st/common/stm32mp_gic.c
48 BL32_SOURCES += plat/st/common/stm32mp_svc_setup.c \
49 plat/st/stm32mp1/services/bsec_svc.c \
50 plat/st/stm32mp1/services/stm32mp1_svc_setup.c \
51 plat/st/stm32mp1/stm32mp1_scmi.c
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/constraints/
H A Dmt_spm_rc_bus26m.c113 const struct rc_common_state *st; in spm_update_rc_bus26m() local
115 st = (const struct rc_common_state *)val; in spm_update_rc_bus26m()
117 if (!st) in spm_update_rc_bus26m()
120 if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_bus26m()
121 (st->type == CONSTRAINT_RESIDNECY)) in spm_update_rc_bus26m()
122 spm_rc_constraint_status_set(st->id, in spm_update_rc_bus26m()
123 st->type, st->act, in spm_update_rc_bus26m()
125 st->value, in spm_update_rc_bus26m()
129 __func__, __LINE__, st->type); in spm_update_rc_bus26m()
241 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_bus26m() local
[all …]
H A Dmt_spm_rc_syspll.c113 const struct rc_common_state *st; in spm_update_rc_syspll() local
115 st = (const struct rc_common_state *)val; in spm_update_rc_syspll()
117 if (!st) in spm_update_rc_syspll()
119 if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_syspll()
120 (st->type == CONSTRAINT_RESIDNECY)) in spm_update_rc_syspll()
121 spm_rc_constraint_status_set(st->id, st->type, in spm_update_rc_syspll()
122 st->act, in spm_update_rc_syspll()
124 st->value, in spm_update_rc_syspll()
128 __func__, __LINE__, st->type); in spm_update_rc_syspll()
246 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_syspll() local
[all …]
H A Dmt_spm_rc_vcore.c109 const struct rc_common_state *st; in spm_update_rc_vcore() local
111 st = (const struct rc_common_state *)val; in spm_update_rc_vcore()
113 if (!st) in spm_update_rc_vcore()
116 if ((st->type == CONSTRAINT_UPDATE_VALID) || in spm_update_rc_vcore()
117 (st->type == CONSTRAINT_RESIDNECY)) in spm_update_rc_vcore()
118 spm_rc_constraint_status_set(st->id, in spm_update_rc_vcore()
119 st->type, st->act, in spm_update_rc_vcore()
121 st->value, in spm_update_rc_vcore()
125 __func__, __LINE__, st->type); in spm_update_rc_vcore()
239 struct rc_common_state *st = (struct rc_common_state *)priv; in spm_get_status_rc_vcore() local
[all …]
/rk3399_ARM-atf/tools/renesas/rza/rza3m/
H A Drz_image.pl53 my @st = stat($origin);
56 my $size = ($st[7] + 3) & "0xfffffffffffffffc";
58 if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";}
89 read($origin, $buf, $st[7]);
91 if($st[7] < $size) {
92 warn "Not aligned. Append " . ($size-$st[7]) . " zero(s)";
94 for(;$st[7] < $size; $size--) {

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