1# 2# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14# Disable PIE by default. To re-enable it, uncomment next line. 15#ENABLE_PIE := 1 16PROGRAMMABLE_RESET_ADDRESS := 1 17ifeq ($(ENABLE_PIE),1) 18BL2_IN_XIP_MEM := 1 19endif 20 21STM32MP_BL33_EL1 ?= 1 22ifeq ($(STM32MP_BL33_EL1),1) 23INIT_UNUSED_NS_EL2 := 1 24endif 25 26# Disable features unsupported in ARMv8.0 27ENABLE_SPE_FOR_NS := 0 28ENABLE_SVE_FOR_NS := 0 29 30# Default Device tree 31DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 32 33TF_CFLAGS += -DSTM32MP2X 34 35STM32MP21 ?= 0 36STM32MP23 ?= 0 37STM32MP25 ?= 0 38 39ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),) 40STM32MP21 := 1 41endif 42ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),) 43STM32MP23 := 1 44endif 45ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),) 46STM32MP25 := 1 47endif 48ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1) 49$(warning STM32MP21=$(STM32MP21)) 50$(warning STM32MP23=$(STM32MP23)) 51$(warning STM32MP25=$(STM32MP25)) 52$(warning DTB_FILE_NAME=$(DTB_FILE_NAME)) 53$(error Cannot enable more than one STM32MP2x flag) 54endif 55 56# STM32 image header version v2.2 or v2.3 for STM32MP21 57STM32_HEADER_VERSION_MAJOR := 2 58ifeq ($(STM32MP21),1) 59STM32_HEADER_VERSION_MINOR := 3 60else 61STM32_HEADER_VERSION_MINOR := 2 62endif 63 64STM32_HASH_VER := 4 65STM32_RNG_VER := 4 66ifeq ($(STM32MP21),1) 67STM32_RNG_VER_MINOR := 4 68else 69STM32_RNG_VER_MINOR := 3 70endif 71 72# Set load address for serial boot devices 73DWL_BUFFER_BASE ?= 0x87000000 74 75# DDR types 76STM32MP_DDR3_TYPE ?= 0 77STM32MP_DDR4_TYPE ?= 0 78STM32MP_LPDDR4_TYPE ?= 0 79ifeq (${STM32MP_DDR3_TYPE},1) 80DDR_TYPE := ddr3 81endif 82ifeq (${STM32MP_DDR4_TYPE},1) 83DDR_TYPE := ddr4 84endif 85ifeq (${STM32MP_LPDDR4_TYPE},1) 86DDR_TYPE := lpddr4 87endif 88 89# DDR features 90STM32MP_DDR_DUAL_AXI_PORT := 1 91STM32MP_DDR_FIP_IO_STORAGE := 1 92 93# Device tree 94BL2_DTSI := stm32mp25-bl2.dtsi 95FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 96BL31_DTSI := stm32mp25-bl31.dtsi 97FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 98 99# Macros and rules to build TF binary 100STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 101STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 102STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 103 104STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 105STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 106STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 107ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 108STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 109STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 110STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 111endif 112FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 113 114# Add the FW_CONFIG to FIP and specify the same to certtool 115$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 116 117# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 118$(eval $(call TOOL_ADD_IMG_PAYLOAD,STM32MP_SOC_FW_CONFIG,$(STM32MP_SOC_FW_CONFIG),--soc-fw-config,$(patsubst %.dtb,%.dts,$(STM32MP_SOC_FW_CONFIG)))) 119 120ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 121# Add the FW_DDR to FIP and specify the same to certtool 122$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 123endif 124 125# Ultratronik Specific Boards 126ifeq ($(findstring ultra-fly,$(DTB_FILE_NAME)),ultra-fly) 127ULTRA_FLY := 1 128$(eval $(call assert_booleans,\ 129 $(sort \ 130 ULTRA_FLY \ 131 ))) 132$(eval $(call add_defines,\ 133 $(sort \ 134 ULTRA_FLY \ 135 ))) 136endif 137 138# Enable flags for C files 139$(eval $(call assert_booleans,\ 140 $(sort \ 141 STM32MP_DDR_DUAL_AXI_PORT \ 142 STM32MP_DDR_FIP_IO_STORAGE \ 143 STM32MP_DDR3_TYPE \ 144 STM32MP_DDR4_TYPE \ 145 STM32MP_LPDDR4_TYPE \ 146 STM32MP21 \ 147 STM32MP23 \ 148 STM32MP25 \ 149 STM32MP_BL33_EL1 \ 150))) 151 152$(eval $(call assert_numerics,\ 153 $(sort \ 154 PLAT_PARTITION_MAX_ENTRIES \ 155 STM32_HASH_VER \ 156 STM32_HEADER_VERSION_MAJOR \ 157 STM32_RNG_VER \ 158 STM32_RNG_VER_MINOR \ 159 STM32_TF_A_COPIES \ 160))) 161 162$(eval $(call add_defines,\ 163 $(sort \ 164 DWL_BUFFER_BASE \ 165 PLAT_DEF_FIP_UUID \ 166 PLAT_PARTITION_MAX_ENTRIES \ 167 PLAT_TBBR_IMG_DEF \ 168 STM32_HASH_VER \ 169 STM32_RNG_VER \ 170 STM32_RNG_VER_MINOR \ 171 STM32_TF_A_COPIES \ 172 STM32MP_DDR_DUAL_AXI_PORT \ 173 STM32MP_DDR_FIP_IO_STORAGE \ 174 STM32MP_DDR3_TYPE \ 175 STM32MP_DDR4_TYPE \ 176 STM32MP_LPDDR4_TYPE \ 177 STM32MP21 \ 178 STM32MP23 \ 179 STM32MP25 \ 180 STM32MP_BL33_EL1 \ 181))) 182 183# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 184# Disable mbranch-protection to avoid adding useless code 185TF_CFLAGS += -mbranch-protection=none 186 187# Include paths and source files 188PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 189PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 190PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 191 192PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 193PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 194PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 195 196PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 197 drivers/st/pmic/stpmic2.c \ 198 199PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 200 201PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 202 203PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 204 drivers/st/reset/stm32mp2_reset.c \ 205 plat/st/stm32mp2/stm32mp2_syscfg.c 206 207PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 208 drivers/st/clk/clk-stm32mp2.c \ 209 drivers/st/crypto/stm32_rng.c 210 211BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 212 213BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 214 plat/st/stm32mp2/plat_ddr.c 215 216BL2_SOURCES += drivers/st/crypto/stm32_hash.c 217 218BL2_SOURCES += drivers/st/rif/stm32_rifsc.c \ 219 drivers/st/rif/stm32mp2_risaf.c 220 221ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 222BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 223endif 224 225ifeq (${STM32MP_USB_PROGRAMMER},1) 226#The DFU stack uses only one end point, reduce the USB stack footprint 227$(eval $(call add_define_val,CONFIG_USBD_EP_NB,1U)) 228$(eval $(call add_define,USB_CORE_AVOID_PACKET_SPLIT_MPS)) 229BL2_SOURCES += drivers/st/usb_dwc3/usb_dwc3.c \ 230 plat/st/stm32mp2/stm32mp2_usb_dfu.c 231endif 232 233BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 234 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 235 drivers/st/ddr/stm32mp2_ram.c 236 237BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 238 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 239 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 240 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 241 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 242 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 243 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 244 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 245 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 246 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 247 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 248 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 249 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 250 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 251 252BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 253 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 254 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 255 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 256 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 257 258# BL31 sources 259BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 260 261BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 262 plat/st/stm32mp2/stm32mp2_pm.c \ 263 plat/st/stm32mp2/stm32mp2_topology.c 264# Generic GIC v2 265include drivers/arm/gic/v2/gicv2.mk 266 267BL31_SOURCES += ${GICV2_SOURCES} \ 268 plat/common/plat_gicv2.c \ 269 plat/st/common/stm32mp_gic.c 270 271# Generic PSCI 272BL31_SOURCES += plat/common/plat_psci_common.c 273 274BL31_SOURCES += plat/st/common/stm32mp_svc_setup.c \ 275 plat/st/stm32mp2/services/stgen_svc.c \ 276 plat/st/stm32mp2/services/stm32mp2_svc_setup.c 277 278# Arm Archtecture services 279BL31_SOURCES += services/arm_arch_svc/arm_arch_svc_setup.c 280 281# Compilation rules 282.PHONY: check_ddr_type 283bl2: check_ddr_type 284 285check_ddr_type: 286 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 287 $(STM32MP_DDR4_TYPE) + \ 288 $(STM32MP_LPDDR4_TYPE))))) 289 @if [ ${DDR_TYPE} != 1 ]; then \ 290 echo "One and only one DDR type must be defined"; \ 291 false; \ 292 fi 293 294# Generate separate DDR FIP image 295ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 296ifneq ($(filter 1,${STM32MP_UART_PROGRAMMER} ${STM32MP_USB_PROGRAMMER}),) 297 298STM32MP_DDR_FW_COPY := ${STM32MP_DDR_FW} 299DDR_FIP_NAME ?= fip-ddr.bin 300 301$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW_COPY,--ddr-fw,DDR_)) 302 303${BUILD_PLAT}/${DDR_FIP_NAME}: ${DDR_FIP_DEPS} fiptool 304 ${Q}${FIPTOOL} create ${DDR_FIP_ARGS} $@ 305 ${Q}${FIPTOOL} info $@ 306 @${ECHO_BLANK_LINE} 307 @echo "Built $@ successfully" 308 @${ECHO_BLANK_LINE} 309 310fip-ddr: ${BUILD_PLAT}/${DDR_FIP_NAME} 311 312fip: fip-ddr 313 314endif 315endif 316 317# Create DTB file for BL31 318${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 319 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 320 @echo '#include "${BL31_DTSI}"' >> $@ 321 322include plat/st/common/common_rules.mk 323