| #
c8e1a2d9 |
| 29-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes Ic735cd1c,Iba4cdbf5,I0dd74152,I3a051ca2,Ie413233d, ... into integration
* changes:
feat(stm32mp2): add RIFSC/RISAB protection for USB3DR
feat(st-drivers): add RIFSC driver
feat(s
Merge changes Ic735cd1c,Iba4cdbf5,I0dd74152,I3a051ca2,Ie413233d, ... into integration
* changes:
feat(stm32mp2): add RIFSC/RISAB protection for USB3DR
feat(st-drivers): add RIFSC driver
feat(stm32mp2): add STM32MP_USB_PROGRAMMER support
feat(stm32mp2): generate FIP for DDR initialization
feat(stm32mp2): add support for minimal FIP with only DDR FW
fix(st): allow several call of stm32cubeprog_uart_load
feat(st): update stm32cubeprogrammer API
feat(stm32mp1): add stm32_get_uid_otp
feat(st-usb): add USB DWC3 driver
fix(st): replace down counter by a timeout upon dfu detach
show more ...
|
| #
8934c7b0 |
| 26-Feb-2025 |
Maxime Méré <maxime.mere@foss.st.com> |
feat(st-drivers): add RIFSC driver
RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:
-RISC registers(slave periph
feat(st-drivers): add RIFSC driver
RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:
-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.
This doesn't support semaphore acquisition.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iba4cdbf53243292fa0b42cad8392c43734dd9bc2
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|
| #
6d1366e5 |
| 19-Sep-2024 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp2): add STM32MP_USB_PROGRAMMER support
Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.
feat(stm32mp2): add STM32MP_USB_PROGRAMMER support
Add STM32MP_USB_PROGRAMMER support for STM32MP2 platform by
compiling usb-dwc3 driver and adding the requested memory and
USB-DFU configurations.
The DFU stack is used in BL2 when STM32MP_USB_PROGRAMMER is activated
by the STMicroelectronics tools STM32Cubeprogrammer for serial boot mode
on USB.
Change-Id: I0dd74152ee6e0a3a3d1332d4fb2edbae7743fcc1
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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|
| #
aa63c231 |
| 12-May-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp2): generate FIP for DDR initialization
Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.
It is loaded in internal memory
feat(stm32mp2): generate FIP for DDR initialization
Generate a minimal FIP used for DDR initialization for serial boot
when STM32MP_DDR_FIP_IO_STORAGE is activated.
It is loaded in internal memory before to be used with support of
the FIP memmap.
To ease Trusted Boot porting for serial boot, we can use TOOL_ADD_IMG
with a DDR_ prefix. To avoid the overriding rule issue with the check
rule in TOOL_ADD_IMG, a copy of the STM32MP_DDR_FW variable is created.
Change-Id: I3a051ca2b258771e48c6e9fed9d77ab512c2416f
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
show more ...
|
| #
7f690c37 |
| 04-Aug-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration
* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encr
Merge changes Ib220a866,I38e6af65,I1554efdb,Iae99985e,I96f96267, ... into integration
* changes:
feat(stm32mp25-fdts): enable rng nodes for ST boards
feat(stm32mp2): prepare DDR secure area encryption
feat(stm32mp2): add some platform helpers
feat(st-drivers): add RISAF driver
feat(fdts): add RISAF nodes for STM32MP25
feat(stm32mp2-fdts): add memory firewall node
feat(stm32mp2-fdts): add firewall nodes in fw-config
feat(stm32mp2): add RIF dt-binding defines
feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board
feat(stm32mp1): prepare DDR secure area encryption for STM32MP13
feat(stm32mp1): enable MCE driver for STM32MP13
feat(st-drivers): add Memory Cipher Engine driver
feat(dt-bindings): add MCE DT bindings for STM32MP13
fix(st-crypto): improve RNG health test configuration
feat(st): add RNG minor version
feat(st-crypto): add multi instance and error management in RNG driver
feat(stm32mp2): add HASH and RNG compilation
feat(stm32mp25-fdts): add RNG node
show more ...
|
| #
399cfdd4 |
| 20-Jan-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-drivers): add RISAF driver
Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t
feat(st-drivers): add RISAF driver
Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.
The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2
show more ...
|
| #
864466be |
| 20-Nov-2024 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
feat(st): add RNG minor version
Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608
feat(st): add RNG minor version
Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608bd5cad77616bf0c031c66a8312b65d3e68c5
show more ...
|
| #
27b4244b |
| 20-Apr-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp2): add HASH and RNG compilation
Add the drivers compilation in STM32MP2 platform.mk.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892
feat(stm32mp2): add HASH and RNG compilation
Add the drivers compilation in STM32MP2 platform.mk.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892eff66c99
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|
| #
4f6c787e |
| 09-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family
show more ...
|
| #
701178dc |
| 01-Aug-2024 |
Maxime Méré <maxime.mere@foss.st.com> |
feat(st): introduce SoC family compilation switch
add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1
feat(st): introduce SoC family compilation switch
add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.
This will avoid to forget to modify all these files when a new SoC is
introduced.
Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
show more ...
|
| #
e577ca36 |
| 02-Feb-2024 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
docs(stm32mp2): introduce new STM32MP23 family
STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
docs(stm32mp2): introduce new STM32MP23 family
STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
H264 - 3D GPU - AI / NN - LVDS / DSI
- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
Change-Id: Iaf3dd7e0c1eda055063361af3c98855b1272d4c6
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| #
07759f2b |
| 20-Apr-2023 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(stm32mp2): introduce new STM32MP21 family
STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
docs(stm32mp2): introduce new STM32MP21 family
STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
CSI - LTDC
- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
Change-Id: Ie3db430bedd86c3b444bec647792be24b20a0cba
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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|
| #
db7770ed |
| 04-Apr-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "upstream-stm32mp257d-ultra-fly-sbc" into integration
* changes:
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
feat(fdts): add support for STM32MP257D
Merge changes from topic "upstream-stm32mp257d-ultra-fly-sbc" into integration
* changes:
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
feat(fdts): add support for STM32MP257D-based ultra-fly-sbc board
feat(fdts): add dual-ranked LPDDR4 config for STM32MP2
show more ...
|
| #
d59dd96d |
| 01-Apr-2025 |
Boerge Struempfel <boerge.struempfel@gmail.com> |
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these bo
feat(stm32mp2): use USART1 for debug console on ultra-fly boards
This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these boards.
These changes are specific to the ultra-fly boards and do not
affect any other boards.
Change-Id: I17f2c50779426dc31a8e85d6903141c331882c86
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
show more ...
|
| #
9da0ba8e |
| 27-Feb-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes Ie8c83c92,I9cca19fd into integration
* changes:
feat(stm32mp2): disable PIE by default on STM32MP2 platform
refactor(stm32mp2): remove useless STM32MP_SEC_SYSRAM_SIZE
|
| #
ac9abe7e |
| 10-Dec-2024 |
Maxime Méré <maxime.mere@foss.st.com> |
feat(stm32mp2): disable PIE by default on STM32MP2 platform
Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by defaul
feat(stm32mp2): disable PIE by default on STM32MP2 platform
Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning
of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by default.
This should allow us to reduce BL31 and BL2 size.
Change-Id: Ie8c83c9205e81301eb1fdcf24b94216172586630
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
show more ...
|
| #
9e6ab88e |
| 16-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration
* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32
Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration
* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32mp1): rework SVC services
show more ...
|
| #
7f41506f |
| 27-Jul-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
feat(stm32mp2): add a runtime service for STGEN configuration
Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Th
feat(stm32mp2): add a runtime service for STGEN configuration
Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69
show more ...
|
| #
f55b136a |
| 27-Jul-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
feat(stm32mp2): add common SMC runtime services
Implement the common SMC runtime services for stm32mp2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Max
feat(stm32mp2): add common SMC runtime services
Implement the common SMC runtime services for stm32mp2 platforms.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9
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|
| #
f340f3d8 |
| 27-Nov-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration
* changes:
build: use parameters in calls to `MAKE_DEP`
build: disable suffix rules globally
build: use full paths for generated li
Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration
* changes:
build: use parameters in calls to `MAKE_DEP`
build: disable suffix rules globally
build: use full paths for generated libraries
show more ...
|
| #
daab00cf |
| 03-Sep-2024 |
Chris Kay <chris.kay@arm.com> |
build: disable suffix rules globally
This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occas
build: disable suffix rules globally
This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occasionally conflict with our rules.
Change-Id: I9e023edbc01b5ae48a96fa1078d0b81faabb0cb9
Signed-off-by: Chris Kay <chris.kay@arm.com>
show more ...
|
| #
a4fe3846 |
| 15-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge "fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT" into integration
|
| #
f15f1c62 |
| 14-Nov-2024 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT
Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binari
fix(stm32mp2): use TOOL_ADD_IMG_PAYLOAD for BL31 DT
Use TOOL_ADD_IMG_PAYLOAD instead of TOOL_ADD_IMG to generate the BL31
device tree blob to be included in FIP. This allows building all TF-A
binaries and FIP in a single command. Else, as TOOL_ADD_IMG evaluate
the existence of the file before building it, we have a build error.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I72d2f70733c49792d0321ad07f5a3bbd283a36d4
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| #
34088d7d |
| 05-Nov-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration
* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported f
Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration
* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported features
show more ...
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| #
c900760d |
| 11-Jan-2024 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp2): boot BL33 at EL1 or EL2
STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_U
feat(stm32mp2): boot BL33 at EL1 or EL2
STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.
Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.
Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
show more ...
|