| /optee_os/core/arch/arm/plat-marvell/ |
| H A D | platform_config.h | 72 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
103 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
122 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
144 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
161 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| /optee_os/core/arch/arm/plat-corstone1000/ |
| H A D | main.c | 20 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
31 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
33 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-imx/ |
| H A D | main.c | 54 #ifdef GICD_BASE
55 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, 0x10000);
110 #ifdef GICD_BASE in boot_primary_init_intc()
111 gic_init(0, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-automotive_rd/ |
| H A D | main.c | 21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
34 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
39 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 31 #define GICD_BASE UL(0x20000000) macro
58 #define GICD_BASE UL(0x30000000) macro
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| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | platform_config.h | 23 #define GICD_BASE (GIC_BASE + 0x1000) macro
52 #define GICD_BASE GIC_BASE macro
74 #define GICD_BASE (GIC_BASE + 0x1000) macro
94 #define GICD_BASE GIC_BASE macro
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| /optee_os/core/arch/arm/plat-aspeed/ |
| H A D | platform_ast2700.c | 15 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
24 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 27 #define GICD_BASE 0x12200000 macro
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| /optee_os/core/arch/arm/plat-versal2/ |
| H A D | main.c | 29 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
36 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-qcom/ |
| H A D | main.c | 21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
48 gic_init_v3(0, GICD_BASE, GICR_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 30 #define GICD_BASE UL(0x17a00000) macro
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| /optee_os/core/arch/arm/plat-bcm/ |
| H A D | platform_config.h | 18 #define GICD_BASE 0x63c00000 macro
54 #define BCM_DEVICE0_BASE GICD_BASE
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| /optee_os/core/arch/arm/plat-rcar/ |
| H A D | platform_config.h | 43 #define GICD_BASE 0xF1010000 macro
52 #define GICD_BASE 0xF1000000 macro
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| H A D | main.c | 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
92 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-ti/ |
| H A D | platform_config.h | 45 #define GICD_BASE (SCU_BASE + GICD_OFFSET) macro
80 #define GICD_BASE (SCU_BASE + GICD_OFFSET) macro
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| /optee_os/core/arch/arm/plat-nuvoton/ |
| H A D | main.c | 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
60 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| H A D | platform_config.h | 22 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| /optee_os/core/arch/arm/plat-k3/ |
| H A D | main.c | 24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE);
48 gic_init(GICC_BASE, GICD_BASE); in boot_primary_init_intc()
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| /optee_os/core/arch/arm/plat-imx/registers/ |
| H A D | imx95.h | 8 #define GICD_BASE 0x48000000 macro
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| H A D | imx943.h | 8 #define GICD_BASE 0x48000000 macro
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| H A D | imx93.h | 8 #define GICD_BASE 0x48000000 macro
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| H A D | imx8q.h | 9 #define GICD_BASE 0x51a00000 macro
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| H A D | imx8ulp.h | 10 #define GICD_BASE 0x2d400000 macro
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| /optee_os/core/arch/arm/plat-rzn1/ |
| H A D | platform_config.h | 20 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 42 #define GICD_BASE (GIC_BASE + GICD_OFFSET) macro
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