19781fbd2SClement Faure /* SPDX-License-Identifier: BSD-2-Clause */ 29781fbd2SClement Faure /* 39781fbd2SClement Faure * Copyright 2021 NXP 49781fbd2SClement Faure */ 59781fbd2SClement Faure #ifndef __IMX8ULP_H__ 69781fbd2SClement Faure #define __IMX8ULP_H__ 79781fbd2SClement Faure 89781fbd2SClement Faure #include <registers/imx8ulp-crm.h> 99781fbd2SClement Faure 109781fbd2SClement Faure #define GICD_BASE 0x2d400000 119781fbd2SClement Faure #define GICR_BASE 0x2d440000 129781fbd2SClement Faure #define UART4_BASE 0x29390000 139781fbd2SClement Faure #define UART5_BASE 0x293a0000 149781fbd2SClement Faure #define CAAM_BASE 0x292e0000 152866fd96SClement Faure #define CAAM_SIZE 0x10000 169781fbd2SClement Faure #define PCC3_BASE 0x292d0000 179781fbd2SClement Faure #define PCC3_SIZE 0x1000 189781fbd2SClement Faure #define AIPS3_BASE 0x29000000 199781fbd2SClement Faure #define AIPS3_SIZE 0x400000 209781fbd2SClement Faure #define SECMEM_BASE 0x00100000 219781fbd2SClement Faure #define SECMEM_SIZE 0x80000 22*4f89aed3SClement Faure #define MU_BASE 0x27020000 23*4f89aed3SClement Faure #define MU_SIZE 0x10000 249781fbd2SClement Faure 259781fbd2SClement Faure #endif /* __IMX8ULP_H__ */ 26