1*1e219620SSumit Garg // SPDX-License-Identifier: BSD-2-Clause
2*1e219620SSumit Garg /*
3*1e219620SSumit Garg * Copyright (c) 2025, Linaro Limited
4*1e219620SSumit Garg * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5*1e219620SSumit Garg */
6*1e219620SSumit Garg
7*1e219620SSumit Garg #include <console.h>
8*1e219620SSumit Garg #include <drivers/gic.h>
9*1e219620SSumit Garg #include <drivers/qcom_geni_uart.h>
10*1e219620SSumit Garg #include <kernel/boot.h>
11*1e219620SSumit Garg #include <mm/core_mmu.h>
12*1e219620SSumit Garg #include <platform_config.h>
13*1e219620SSumit Garg
14*1e219620SSumit Garg /*
15*1e219620SSumit Garg * Register the physical memory area for peripherals etc. Here we are
16*1e219620SSumit Garg * registering the UART console.
17*1e219620SSumit Garg */
18*1e219620SSumit Garg register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GENI_UART_REG_BASE,
19*1e219620SSumit Garg GENI_UART_REG_SIZE);
20*1e219620SSumit Garg
21*1e219620SSumit Garg register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
22*1e219620SSumit Garg register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
23*1e219620SSumit Garg
24*1e219620SSumit Garg register_ddr(DRAM0_BASE, DRAM0_SIZE);
25*1e219620SSumit Garg #ifdef DRAM1_BASE
26*1e219620SSumit Garg register_ddr(DRAM1_BASE, DRAM1_SIZE);
27*1e219620SSumit Garg #endif
28*1e219620SSumit Garg
29*1e219620SSumit Garg static struct qcom_geni_uart_data console_data;
30*1e219620SSumit Garg
plat_console_init(void)31*1e219620SSumit Garg void plat_console_init(void)
32*1e219620SSumit Garg {
33*1e219620SSumit Garg qcom_geni_uart_init(&console_data, GENI_UART_REG_BASE);
34*1e219620SSumit Garg register_serial_console(&console_data.chip);
35*1e219620SSumit Garg }
36*1e219620SSumit Garg
boot_primary_init_intc(void)37*1e219620SSumit Garg void boot_primary_init_intc(void)
38*1e219620SSumit Garg {
39*1e219620SSumit Garg gic_init_v3(0, GICD_BASE, GICR_BASE);
40*1e219620SSumit Garg }
41*1e219620SSumit Garg
boot_secondary_init_intc(void)42*1e219620SSumit Garg void boot_secondary_init_intc(void)
43*1e219620SSumit Garg {
44*1e219620SSumit Garg gic_init_per_cpu();
45*1e219620SSumit Garg }
46