plat-ti: Add SM handler for setting AMBA IF in the WUGEN

This mirrors what is available as a ROM API. We implement this here as
OP-TEE's monitor replaces the ROM's monitor functions and we would lik

plat-ti: Add SM handler for setting AMBA IF in the WUGEN

This mirrors what is available as a ROM API. We implement this here as
OP-TEE's monitor replaces the ROM's monitor functions and we would like
to keep feature parity.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Disable SECURE_DATA_PATH until xtest is fixed

While SDP support is being re-worked disable support by default to
prevent failing test cases. This will be re-enabled when the REE-side
suppor

plat-ti: Disable SECURE_DATA_PATH until xtest is fixed

While SDP support is being re-worked disable support by default to
prevent failing test cases. This will be re-enabled when the REE-side
support is restored.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP

core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.

This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().

In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: move some CFG_'s from platform_config.h to conf.mk

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew F. Davis <afd@ti.com>

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura

core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config

core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c

core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BA

core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BASE/_SIZE is a generic configuration directive to
register a SDP memory.

Some platforms define a SDP test memory when SDP is enable. This SDP
memory is located at the end of the TA_RAM. Introduce platform settings
TEE_SDP_TEST_MEM_BASE/_SIZE to register a SDP test buffer, independently
from the generic CFG_TEE_SDP_MEM_BASE/_SIZE.

Platforms marvel, stm, ti and vexpress updated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Reserve first page of SRAM for secure boot software

The first 4KB of SRAM is used by the initial secure software and
OP-TEE should not be loaded to this address. Adjust the TEE_LOAD_ADDR
to

plat-ti: Reserve first page of SRAM for secure boot software

The first 4KB of SRAM is used by the initial secure software and
OP-TEE should not be loaded to this address. Adjust the TEE_LOAD_ADDR
to reflect this.

Signed-off-by: Andrew F. Davis <afd@ti.com>

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plat-ti: Remove start address offset from base of TEE_RAM start

We offset our start address from the start of TEE_RAM_START, this
was to allow in-place loading while keeping the OPTEE header inside

plat-ti: Remove start address offset from base of TEE_RAM start

We offset our start address from the start of TEE_RAM_START, this
was to allow in-place loading while keeping the OPTEE header inside
secure memory. This is not needed anymore as we relocate the image.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Add secure paging support for DRA7xx/AM57xx

Add definitions for secure SRAM and DRAM space for builds with
CFG_WITH_PAGER enabled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jen

plat-ti: Add secure paging support for DRA7xx/AM57xx

Add definitions for secure SRAM and DRAM space for builds with
CFG_WITH_PAGER enabled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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am57xx: fix build error

Fix "#elif with no expression" error when building with ti-am57xx flavor
Add am57xx to .travic.yml as supported platform

Reviewed-by: Jerome Forissier <jerome.forissier@lina

am57xx: fix build error

Fix "#elif with no expression" error when building with ti-am57xx flavor
Add am57xx to .travic.yml as supported platform

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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plat-ti: Add AM43xx platform flavor

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

plat-ti: Cleanup platform configuration

Reorganize platform configuration to assist in addition of new
platforms. No functional changes.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joa

plat-ti: Cleanup platform configuration

Reorganize platform configuration to assist in addition of new
platforms. No functional changes.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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plat-ti: Move TZDRAM area to better align with other DRAM uses

The area currently reserved for OP-TEE overlaps an area that is used
by another existing device use-case, move OP-TEE to a non-interfer

plat-ti: Move TZDRAM area to better align with other DRAM uses

The area currently reserved for OP-TEE overlaps an area that is used
by another existing device use-case, move OP-TEE to a non-interfering
address.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecate

core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecated since platform should use the more flexible
register_phys_mem() macro.

This change removes all occurrences of DEVICEx_TYPE/_PA_BASE/_SIZE
and use the register_phys_mem() instead.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Add AM57xx platform flavor

The AM57xx flavor is based on DRA7xx except that it uses a
different UART port. Add this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jerome Fo

plat-ti: Add AM57xx platform flavor

The AM57xx flavor is based on DRA7xx except that it uses a
different UART port. Add this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ti: Enable GIC driver support for DRA7xx

The DRA7xx platform contains a standard GICv2. Enable this driver.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklan

plat-ti: Enable GIC driver support for DRA7xx

The DRA7xx platform contains a standard GICv2. Enable this driver.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.

drivers: Add TRNG driver for DRA7

Add driver for the True Random Number Generator (TRNG) available
on DRA7xx platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based p

plat-ti: Move load address and increase SHMEM

Move and expand the shared memory allocation as suggested
by the comment above the definition. This should be a safe
place and size for all DRA7 based platforms.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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