1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024 - 2025, Arm Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 #include <util.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 #if defined(PLATFORM_FLAVOR_rdaspen) 16 17 /* DRAM constants */ 18 #define DRAM0_BASE UL(0x80000000) 19 #define DRAM0_SIZE SIZE_2G 20 #define DRAM1_BASE ULL(0x20000000000) 21 #define DRAM1_SIZE SIZE_2G 22 23 /* UART constants */ 24 #define UART_BAUDRATE 115200 25 #define CONSOLE_BAUDRATE UART_BAUDRATE 26 #define UART1_BASE UL(0x1a410000) 27 #define CONSOLE_UART_BASE UART1_BASE 28 #define CONSOLE_UART_CLK_IN_HZ UL(24000000) 29 30 /* GIC related constants */ 31 #define GICD_BASE UL(0x20000000) 32 #define GICR_BASE UL(0x200C0000) 33 #define GICR_SIZE UL(0xF00000) 34 35 /* RD-Aspen topology related constants */ 36 #define RDASPEN_MAX_CPUS_PER_CLUSTER U(4) 37 #define RDASPEN_MAX_PE_PER_CPU U(1) 38 39 #elif defined(PLATFORM_FLAVOR_rd1ae) 40 41 /* DRAM constants */ 42 #define DRAM0_BASE UL(0x80000000) 43 #define DRAM0_SIZE SIZE_2G 44 45 #define DRAM1_BASE ULL(0x8080000000) 46 #define DRAM1_SIZE SIZE_2G 47 48 #define SYS_COUNTER_FREQ_IN_TICKS UL(7372800) 49 /* UART constants */ 50 #define UART_BAUDRATE 115200 51 #define CONSOLE_BAUDRATE UART_BAUDRATE 52 #define UART0_BASE UL(0x2A400000) 53 #define UART1_BASE UL(0x2A410000) 54 #define CONSOLE_UART_BASE UART1_BASE 55 #define CONSOLE_UART_CLK_IN_HZ UL(7372800) 56 57 /* GIC related constants */ 58 #define GICD_BASE UL(0x30000000) 59 #define GICC_BASE UL(0x2C000000) 60 61 /* RD-1 AE topology related constants */ 62 #define RD1AE_MAX_CPUS_PER_CLUSTER U(1) 63 #define RD1AE_MAX_CLUSTERS_PER_CHIP U(16) 64 65 #else 66 #error "Unknown platform flavor" 67 #endif 68 69 #endif /* PLATFORM_CONFIG_H */ 70