xref: /optee_os/core/arch/arm/plat-versal2/main.c (revision 59a0f5d07e726c2c2c9470618f804aa3d5004e34)
1*59a0f5d0SAkshay Belsare // SPDX-License-Identifier: BSD-2-Clause
2*59a0f5d0SAkshay Belsare /*
3*59a0f5d0SAkshay Belsare  * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
4*59a0f5d0SAkshay Belsare  */
5*59a0f5d0SAkshay Belsare 
6*59a0f5d0SAkshay Belsare #include <arm.h>
7*59a0f5d0SAkshay Belsare #include <assert.h>
8*59a0f5d0SAkshay Belsare #include <console.h>
9*59a0f5d0SAkshay Belsare #include <drivers/gic.h>
10*59a0f5d0SAkshay Belsare #include <drivers/pl011.h>
11*59a0f5d0SAkshay Belsare #include <drivers/versal_pm.h>
12*59a0f5d0SAkshay Belsare #include <io.h>
13*59a0f5d0SAkshay Belsare #include <kernel/boot.h>
14*59a0f5d0SAkshay Belsare #include <kernel/misc.h>
15*59a0f5d0SAkshay Belsare #include <kernel/tee_time.h>
16*59a0f5d0SAkshay Belsare #include <mm/core_memprot.h>
17*59a0f5d0SAkshay Belsare #include <platform_config.h>
18*59a0f5d0SAkshay Belsare #include <stdint.h>
19*59a0f5d0SAkshay Belsare #include <string.h>
20*59a0f5d0SAkshay Belsare #include <tee/tee_fs.h>
21*59a0f5d0SAkshay Belsare #include <trace.h>
22*59a0f5d0SAkshay Belsare 
23*59a0f5d0SAkshay Belsare static struct pl011_data console_data;
24*59a0f5d0SAkshay Belsare 
25*59a0f5d0SAkshay Belsare register_phys_mem_pgdir(MEM_AREA_IO_SEC,
26*59a0f5d0SAkshay Belsare 			ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
27*59a0f5d0SAkshay Belsare 			CORE_MMU_PGDIR_SIZE);
28*59a0f5d0SAkshay Belsare 
29*59a0f5d0SAkshay Belsare register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
30*59a0f5d0SAkshay Belsare register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
31*59a0f5d0SAkshay Belsare 
32*59a0f5d0SAkshay Belsare register_ddr(DRAM0_BASE, DRAM0_SIZE);
33*59a0f5d0SAkshay Belsare 
boot_primary_init_intc(void)34*59a0f5d0SAkshay Belsare void boot_primary_init_intc(void)
35*59a0f5d0SAkshay Belsare {
36*59a0f5d0SAkshay Belsare 	gic_init_v3(0, GICD_BASE, GICR_BASE);
37*59a0f5d0SAkshay Belsare }
38*59a0f5d0SAkshay Belsare 
plat_console_init(void)39*59a0f5d0SAkshay Belsare void plat_console_init(void)
40*59a0f5d0SAkshay Belsare {
41*59a0f5d0SAkshay Belsare 	pl011_init(&console_data, CONSOLE_UART_BASE,
42*59a0f5d0SAkshay Belsare 		   CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
43*59a0f5d0SAkshay Belsare 	register_serial_console(&console_data.chip);
44*59a0f5d0SAkshay Belsare }
45*59a0f5d0SAkshay Belsare 
platform_banner(void)46*59a0f5d0SAkshay Belsare static TEE_Result platform_banner(void)
47*59a0f5d0SAkshay Belsare {
48*59a0f5d0SAkshay Belsare 	IMSG("OP-TEE OS Running on Platform AMD Versal Gen 2");
49*59a0f5d0SAkshay Belsare 
50*59a0f5d0SAkshay Belsare 	return TEE_SUCCESS;
51*59a0f5d0SAkshay Belsare }
52*59a0f5d0SAkshay Belsare 
53*59a0f5d0SAkshay Belsare service_init(platform_banner);
54