1*4936f055SAhmed Tiba // SPDX-License-Identifier: BSD-2-Clause
2*4936f055SAhmed Tiba /*
3*4936f055SAhmed Tiba * Copyright (c) 2024 - 2025, Arm Limited
4*4936f055SAhmed Tiba */
5*4936f055SAhmed Tiba
6*4936f055SAhmed Tiba #include <console.h>
7*4936f055SAhmed Tiba #include <drivers/gic.h>
8*4936f055SAhmed Tiba #include <drivers/pl011.h>
9*4936f055SAhmed Tiba #include <kernel/boot.h>
10*4936f055SAhmed Tiba #include <mm/core_mmu.h>
11*4936f055SAhmed Tiba #include <platform_config.h>
12*4936f055SAhmed Tiba #include <stdint.h>
13*4936f055SAhmed Tiba #include <trace.h>
14*4936f055SAhmed Tiba
15*4936f055SAhmed Tiba static struct pl011_data console_data __nex_bss;
16*4936f055SAhmed Tiba
17*4936f055SAhmed Tiba register_ddr(DRAM0_BASE, DRAM0_SIZE);
18*4936f055SAhmed Tiba register_ddr(DRAM1_BASE, DRAM1_SIZE);
19*4936f055SAhmed Tiba
20*4936f055SAhmed Tiba register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
21*4936f055SAhmed Tiba register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
22*4936f055SAhmed Tiba
23*4936f055SAhmed Tiba #if defined(PLATFORM_FLAVOR_rd1ae)
24*4936f055SAhmed Tiba register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
25*4936f055SAhmed Tiba #endif
26*4936f055SAhmed Tiba
27*4936f055SAhmed Tiba #if defined(PLATFORM_FLAVOR_rdaspen)
28*4936f055SAhmed Tiba register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
29*4936f055SAhmed Tiba #endif
30*4936f055SAhmed Tiba
boot_primary_init_intc(void)31*4936f055SAhmed Tiba void boot_primary_init_intc(void)
32*4936f055SAhmed Tiba {
33*4936f055SAhmed Tiba #if defined(PLATFORM_FLAVOR_rd1ae)
34*4936f055SAhmed Tiba gic_init(GICC_BASE, GICD_BASE);
35*4936f055SAhmed Tiba #endif
36*4936f055SAhmed Tiba
37*4936f055SAhmed Tiba #if defined(PLATFORM_FLAVOR_rdaspen)
38*4936f055SAhmed Tiba /* GICC_BASE is not required for GICv3 */
39*4936f055SAhmed Tiba gic_init_v3(0, GICD_BASE, GICR_BASE);
40*4936f055SAhmed Tiba #endif
41*4936f055SAhmed Tiba }
42*4936f055SAhmed Tiba
43*4936f055SAhmed Tiba #if defined(PLATFORM_FLAVOR_rd1ae)
boot_secondary_init_intc(void)44*4936f055SAhmed Tiba void boot_secondary_init_intc(void)
45*4936f055SAhmed Tiba {
46*4936f055SAhmed Tiba gic_init_per_cpu();
47*4936f055SAhmed Tiba }
48*4936f055SAhmed Tiba #endif
49*4936f055SAhmed Tiba
plat_console_init(void)50*4936f055SAhmed Tiba void plat_console_init(void)
51*4936f055SAhmed Tiba {
52*4936f055SAhmed Tiba pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
53*4936f055SAhmed Tiba CONSOLE_BAUDRATE);
54*4936f055SAhmed Tiba register_serial_console(&console_data.chip);
55*4936f055SAhmed Tiba }
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