core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-rcar: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Volodymyr Babchuk <vol

plat-rcar: use gic_init_per_cpu()

Call gic_init_per_cpu() instead of the now deprecated gic_cpu_init().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-o

core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by rena

core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by renameing to
boot_secondary_init_intc(), since interrupt controllers are always
initialized in boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic()

core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic() to secondary_init_intc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This

core: define main interrupt controller data from its driver

All but one platforms define CPU core interrupt controller from their
platform main.c source file next to its main interrupt handler.
This change factorize these implementation by moving the definition
of the controller data instance straight in the controller driver
source file. This change makes each controller driver to implement
straight itr_core_handler() function, preventing a extra branch on
interrupt execution. Interrupt controller driver initialization
function now straight calls itr_core_init().

This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable
to not conflict with core/arch/arm/kernel/thread.c that already
overrides itr_core_handler() weak implementation.

With this change, the main controller initialization function
(gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init())
no more gets the controller data as input argument.

As a consequence, definition of struct hfic_data and struct gic_data
moves from their respective driver header file to the respective
driver source file.

As a consequence, gic_dump() no more requires an argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plar: rcar: Use common crypto_rng_read() over hw_get_random_byte()

This has the same effect and removes the last user of
hw_get_random_byte() allowing us to start converting platforms
to hw_get_rand

plar: rcar: Use common crypto_rng_read() over hw_get_random_byte()

This has the same effect and removes the last user of
hw_get_random_byte() allowing us to start converting platforms
to hw_get_random_bytes() and removing hw_get_random_byte().

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plar: rcar: add initial support for Gen4

RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with G

plar: rcar: add initial support for Gen4

RCar Gen4 is the next generation of Renesas automotive
chips. Currently only RCar S4 on board Spider is available. This
platform has 8 CortexA55 cores with GICv3.

This is patch adds minimal support, so not all Gen4 features are
available. Namely, ROM API is not supported right now, so HW RNG and
ASLR are disabled. Also, ATF does not provide DTB, so non-secure DDR
ranges are hardcoded.

Apart from that, depending on external configuration, initial
bootloader can use two different UARTs as console: either SCIF3 or
HSCIF0. Thus, CFG_RCAR_UART is introduced.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: enable GIC support

Enable GIC support in the same as it is done in other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklande

plat: rcar: enable GIC support

Enable GIC support in the same as it is done in other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: enable ASLR

On RCAR hw_get_random_byte() can be called very early, as it have no
dependencies. So we can use it to provide ASLR seed value.

Also, the previous fix to SCIF drivers preven

plat: rcar: enable ASLR

On RCAR hw_get_random_byte() can be called very early, as it have no
dependencies. So we can use it to provide ASLR seed value.

Also, the previous fix to SCIF drivers prevents crashes with ASLR enabled.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: store PRR value in global variable

Product Register will be needed not only by get_core_pos_mpidr
function but by other platform code as well. So move its cached
value into variable in m

plat: rcar: store PRR value in global variable

Product Register will be needed not only by get_core_pos_mpidr
function but by other platform code as well. So move its cached
value into variable in main.c

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk

plat: rcar: use new register_ddr() macro

As register_dynamic_shm() is being retired - switch to the new macro.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
fla

plat: rcar m3: Add support for 8GB version

Add support for M3 SOC with 8GB of RAM. In this case memory is organized in
two bank of 4GB. Renesas calls this variant 2x4g, so in OP-TEE we will have
flavor salvator_m3_2x4g.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar: Obtain memory layout from DT

Since the ATF is passing a DT fragment to OpTee-OS, parse the memory
information from this DT fragment. This makes it possible to run the
OpTee-OS on any mem

plat: rcar: Obtain memory layout from DT

Since the ATF is passing a DT fragment to OpTee-OS, parse the memory
information from this DT fragment. This makes it possible to run the
OpTee-OS on any memory layout instead of the few hard-coded options.
Switch the default platform to this DT based approach, but retain the
legacy platforms as well for backward compatibility.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar: Derive core map from PRR

Instead of hard-coding the core count and the core ID mapping,
derive this information from the PRR register. All R-Car3 SoCs
have either one or two 4-core CPU c

plat: rcar: Derive core map from PRR

Instead of hard-coding the core count and the core ID mapping,
derive this information from the PRR register. All R-Car3 SoCs
have either one or two 4-core CPU clusters composed of CA53 or
CA57, except for M3W/M3W+, which has two CA57s and four CA53s.

So the approach here is to always set core count to 8, read out
PRR register once on boot, and then calculate the core ID using
CorePos = CoreId + (ClusterId << (IsM3W ? 1 : 0))

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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core: remove boot_get_handlers()

struct thread_handlers is used to pass the entry functions
for different power management events. In practice only .cpu_on is used
and with the default function at t

core: remove boot_get_handlers()

struct thread_handlers is used to pass the entry functions
for different power management events. In practice only .cpu_on is used
and with the default function at that. In the ARMv7 case where the
secure monitor replaces TF-A not even that function entry is used.

Remove struct thread_handlers and boot_get_handlers(). When configured
with TF-A initialize thread_*_handler_ptr with __weak default functions.

The __weak default PM functions
- thread_cpu_off_handler()
- thread_cpu_suspend_handler()
- thread_cpu_resume_handler()
- thread_system_off_handler()
- thread_system_reset_handler()
can be overridden by platforms when needed.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove generic_ from generic_boot

Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.

Acked-by: Etienne Carriere <et

core: remove generic_ from generic_boot

Now that the CFG_GENERIC_BOOT configuration flag has been removed also
remove "generic_" prefix from and in the related files.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: replace thread_nintr_handler_ptr with weak function

Removes registration of platform specific secure interrupt handler in
thread_nintr_handler_ptr. Instead a __weak overridable
itr_core_handle

core: replace thread_nintr_handler_ptr with weak function

Removes registration of platform specific secure interrupt handler in
thread_nintr_handler_ptr. Instead a __weak overridable
itr_core_handler() is provided. Platforms which expects to receive
secure interrupts must override the default function. The default
function calls panic() if called.

With this also nintr is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: replace thread_fast_smc_handler_ptr with weak function

Removes registration of platform specific fast SMC entry function in
thread_fast_smc_handler_ptr. Instead a __weak overridable
tee_entry_

core: replace thread_fast_smc_handler_ptr with weak function

Removes registration of platform specific fast SMC entry function in
thread_fast_smc_handler_ptr. Instead a __weak overridable
tee_entry_fast() is provided. Platforms that need a special
tee_entry_fast() (currently on plat-zynq7k) provides their own
tee_entry_fast() instead which at the end should call __tee_entry_fast()
which does the generic fast call handling.

With this also fast_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: replace thread_std_smc_handler_ptr with weak function

Removes registration of platform specific standard SMC entry function in
thread_std_smc_handler_ptr. Instead a __weak overridable tee_entr

core: replace thread_std_smc_handler_ptr with weak function

Removes registration of platform specific standard SMC entry function in
thread_std_smc_handler_ptr. Instead a __weak overridable tee_entry_std()
is provided. Platforms that need a special tee_entry_std() (currently on
some STM platform) provides their own tee_entry_std() instead which at
the end should call __tee_entry_std() which does the generic standard
call handling.

With this also std_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-rcar: virtualization port for RCAR platform

Put platform information into nexus sections, so they are
available at all times.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by

plat-rcar: virtualization port for RCAR platform

Put platform information into nexus sections, so they are
available at all times.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP

core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.

This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().

In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename register_nsec_ddr() to register_dynamic_shm()

register_nsec_ddr() is actually only used to register dynamic physically
non-contiguous SHM, rename it to register_dynamic_shm() will be mo

core: rename register_nsec_ddr() to register_dynamic_shm()

register_nsec_ddr() is actually only used to register dynamic physically
non-contiguous SHM, rename it to register_dynamic_shm() will be more
clear.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Edison Ai <edison.ai@arm.com>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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plat-rcar: add non-secure DDR configuration

This patch adds non-secure DDR ranges for salvator-h3 and
salvator-m3 boards.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wi

plat-rcar: add non-secure DDR configuration

This patch adds non-secure DDR ranges for salvator-h3 and
salvator-m3 boards.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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