xref: /optee_os/core/arch/arm/plat-qcom/main.c (revision 1e2196200255aa75b26cafb6008f0dee69ac2460)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2025, Linaro Limited
4  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5  */
6 
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/qcom_geni_uart.h>
10 #include <kernel/boot.h>
11 #include <mm/core_mmu.h>
12 #include <platform_config.h>
13 
14 /*
15  * Register the physical memory area for peripherals etc. Here we are
16  * registering the UART console.
17  */
18 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GENI_UART_REG_BASE,
19 			GENI_UART_REG_SIZE);
20 
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
23 
24 register_ddr(DRAM0_BASE, DRAM0_SIZE);
25 #ifdef DRAM1_BASE
26 register_ddr(DRAM1_BASE, DRAM1_SIZE);
27 #endif
28 
29 static struct qcom_geni_uart_data console_data;
30 
plat_console_init(void)31 void plat_console_init(void)
32 {
33 	qcom_geni_uart_init(&console_data, GENI_UART_REG_BASE);
34 	register_serial_console(&console_data.chip);
35 }
36 
boot_primary_init_intc(void)37 void boot_primary_init_intc(void)
38 {
39 	gic_init_v3(0, GICD_BASE, GICR_BASE);
40 }
41 
boot_secondary_init_intc(void)42 void boot_secondary_init_intc(void)
43 {
44 	gic_init_per_cpu();
45 }
46