1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2024 - 2025, Arm Limited
4 */
5
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/pl011.h>
9 #include <kernel/boot.h>
10 #include <mm/core_mmu.h>
11 #include <platform_config.h>
12 #include <stdint.h>
13 #include <trace.h>
14
15 static struct pl011_data console_data __nex_bss;
16
17 register_ddr(DRAM0_BASE, DRAM0_SIZE);
18 register_ddr(DRAM1_BASE, DRAM1_SIZE);
19
20 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
22
23 #if defined(PLATFORM_FLAVOR_rd1ae)
24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
25 #endif
26
27 #if defined(PLATFORM_FLAVOR_rdaspen)
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
29 #endif
30
boot_primary_init_intc(void)31 void boot_primary_init_intc(void)
32 {
33 #if defined(PLATFORM_FLAVOR_rd1ae)
34 gic_init(GICC_BASE, GICD_BASE);
35 #endif
36
37 #if defined(PLATFORM_FLAVOR_rdaspen)
38 /* GICC_BASE is not required for GICv3 */
39 gic_init_v3(0, GICD_BASE, GICR_BASE);
40 #endif
41 }
42
43 #if defined(PLATFORM_FLAVOR_rd1ae)
boot_secondary_init_intc(void)44 void boot_secondary_init_intc(void)
45 {
46 gic_init_per_cpu();
47 }
48 #endif
49
plat_console_init(void)50 void plat_console_init(void)
51 {
52 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ,
53 CONSOLE_BAUDRATE);
54 register_serial_console(&console_data.chip);
55 }
56