| /optee_os/core/arch/arm/plat-qcom/ |
| H A D | main.c | 25 #ifdef DRAM1_BASE
26 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| H A D | platform_config.h | 18 #define DRAM1_BASE ULL(0x100000000) macro
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| /optee_os/core/arch/arm/plat-uniphier/ |
| H A D | main.c | 32 #ifdef DRAM1_BASE
33 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-automotive_rd/ |
| H A D | platform_config.h | 20 #define DRAM1_BASE ULL(0x20000000000) macro
45 #define DRAM1_BASE ULL(0x8080000000) macro
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| H A D | main.c | 18 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-telechips/ |
| H A D | main.c | 22 #if defined(DRAM1_BASE)
23 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-hikey/ |
| H A D | platform_config.h | 111 #define DRAM1_BASE CFG_DRAM1_BASE macro
134 #define DRAM1_SIZE_NSEC (0xE0000000 - DRAM1_BASE)
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| H A D | main.c | 38 register_ddr(DRAM1_BASE, DRAM1_SIZE_NSEC);
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| /optee_os/core/arch/arm/plat-stm/ |
| H A D | platform_config.h | 205 #define DRAM1_BASE STM_SECDDR_END macro
206 #define DRAM1_SIZE ((CFG_DDR_START - DRAM1_BASE) + CFG_DDR_SIZE)
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| H A D | main.c | 31 #ifdef DRAM1_BASE
32 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-versal/ |
| H A D | main.c | 44 #if defined(DRAM1_BASE)
45 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| H A D | platform_config.h | 38 #define DRAM1_BASE 0x800000000 macro
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| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | platform_config.h | 103 #define DRAM1_BASE 0x880000000UL macro
124 #define DRAM1_BASE 0x880000000UL macro
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| H A D | main.c | 46 #ifdef DRAM1_BASE
47 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-d02/ |
| H A D | platform_config.h | 70 #define DRAM1_BASE 0x51800000 macro
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| /optee_os/core/arch/arm/plat-totalcompute/ |
| H A D | platform_config.h | 31 #define DRAM1_BASE 0x8080000000ULL macro
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| H A D | main.c | 26 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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| /optee_os/core/arch/arm/plat-zynqmp/ |
| H A D | platform_config.h | 47 #define DRAM1_BASE 0x800000000 macro
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| H A D | main.c | 73 register_ddr(DRAM1_BASE, CFG_DDR_SIZE - 0x80000000);
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| /optee_os/core/arch/arm/plat-telechips/tcc805x/ |
| H A D | platform_config.h | 47 #define DRAM1_BASE U(0x1A0000000) macro
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| /optee_os/core/arch/arm/plat-k3/ |
| H A D | platform_config.h | 21 #define DRAM1_BASE 0x880000000 macro
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| H A D | main.c | 44 register_ddr(DRAM1_BASE, DRAM1_SIZE);
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