plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses

plat-vexpress: add QEMU sbsa-ref platform

Add support for the QEMU sbsa-ref platform. This platform is similar to
the QEMU virt platform, but with different memory configuration and
device addresses.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(

plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(CFG_CORE_SEL2_SPMC=y).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome

plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: fvp: configure GIC redistributor base address

Configure GIC redistributor base address needed with GICv3.

Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
S

plat-vexpress: fvp: configure GIC redistributor base address

Configure GIC redistributor base address needed with GICv3.

Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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qemu_armv8a: add GIC v3 redistributor base address

Adds and configures the GIC v3 redistributor base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <e

qemu_armv8a: add GIC v3 redistributor base address

Adds and configures the GIC v3 redistributor base address.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: remove TPM2 MMIO driver

Disable TPM2 MMIO driver and remove its integration from platform
vexpress. OP-TEE will instead rely on a remote REE TPM2 driver
allowing REE OS to embed TPM2

plat-vexpress: remove TPM2 MMIO driver

Disable TPM2 MMIO driver and remove its integration from platform
vexpress. OP-TEE will instead rely on a remote REE TPM2 driver
allowing REE OS to embed TPM2 software stack and leverage TPM2 features.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-vexpress: qemu: initialize TPM driver

QEMU implements a TPM emulation with TPM TIS/PTP interface. The PTP
interface is exposed via a memory mapped region to the TEE (MMIO
interface).

QEMU TPM

plat-vexpress: qemu: initialize TPM driver

QEMU implements a TPM emulation with TPM TIS/PTP interface. The PTP
interface is exposed via a memory mapped region to the TEE (MMIO
interface).

QEMU TPM emulation can be used with a virtualized TPM2.0 device
(sw-tpm).

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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qemu_v8: configure secure interrupts

Configures GIC and enable reception of interrupts from the secure uart.
This enables testing of secure interrupts on the QEMU v8 platform by
typing in the secure

qemu_v8: configure secure interrupts

Configures GIC and enable reception of interrupts from the secure uart.
This enables testing of secure interrupts on the QEMU v8 platform by
typing in the secure log.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu_*: no need to register non-secure DDR

Qemus force CFG_DT to y resulting in DTB to provide the REE system memory
range(s). No need to register REE memory for dynamic SHM support.

plat-vexpress: qemu_*: no need to register non-secure DDR

Qemus force CFG_DT to y resulting in DTB to provide the REE system memory
range(s). No need to register REE memory for dynamic SHM support.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: move to generic RAM layout

FVP:
- Secure RAM [0600.0000 0800.0000[ configurable.
- Static SHM [8300.0000 8320.0000[ configurable.

Juno:
- Secure RAM [ff00.0000 ffff.8000[ configurabl

plat-vexpress: move to generic RAM layout

FVP:
- Secure RAM [0600.0000 0800.0000[ configurable.
- Static SHM [8300.0000 8320.0000[ configurable.

Juno:
- Secure RAM [ff00.0000 ffff.8000[ configurable.
Note trailing 32kByte reserved by SCP for DDR retraining.
- Static SHM [fee0.0000 ff00.0000[ configurable.

qemu_virt:
- Secure RAM [0e10.0000 0f00.0000[ configurable.
- Static SHM [7fe0.0000 8000.0000[ configurable.

qemu_armv8:
- Secure RAM [0.0e10.0000 0.0f00.0000[ configurable.
- Static SHM [0.ffe0.0000 1.0000.0000[ configurable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu_virt: align DRAM0 end with qemu_armv8

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-vexpress: Juno: don't waste about 2MB of Secure RAM

Only the last 32kByte of the DRAM is used by SCP. There are
a bit less than 2MByte that could be used.

Actually this does not change a lot b

plat-vexpress: Juno: don't waste about 2MB of Secure RAM

Only the last 32kByte of the DRAM is used by SCP. There are
a bit less than 2MByte that could be used.

Actually this does not change a lot but allow to remove a comment
in the platform configuration file.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk

Aggregate juno config.
Use same platform ordering in conf.mk and platform_config.h.

Signed-off-by: Etienne Carriere <etienne.carriere@li

plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk

Aggregate juno config.
Use same platform ordering in conf.mk and platform_config.h.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura

core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config

core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c

core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BA

core: split SDP memory CFG_ and non-CFG_ configuration directives

This change aim at removing definition of CFG_ directive (here related
to SDP) from the platform_config.h files.

CFG_TEE_SDP_MEM_BASE/_SIZE is a generic configuration directive to
register a SDP memory.

Some platforms define a SDP test memory when SDP is enable. This SDP
memory is located at the end of the TA_RAM. Introduce platform settings
TEE_SDP_TEST_MEM_BASE/_SIZE to register a SDP test buffer, independently
from the generic CFG_TEE_SDP_MEM_BASE/_SIZE.

Platforms marvel, stm, ti and vexpress updated.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_virt: move core location to match qemu_armv8

Moving qemu_virt core to the same location as the core for qemu_armv8
allows to use the same arm-trusted-firmware configuration for ARMv7
and ARMv8

qemu_virt: move core location to match qemu_armv8

Moving qemu_virt core to the same location as the core for qemu_armv8
allows to use the same arm-trusted-firmware configuration for ARMv7
and ARMv8 Qemu support.

Qemu_virt Kasan offset is updated since new memory layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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qemu_virt: fix memory configuration

Fixes memory configuration inconsistency introduced with the coherent
memory area for QEMU virt with pager enabled.

Fixes: 5402a9fe46f9 ("qemu_virt: enable smp b

qemu_virt: fix memory configuration

Fixes memory configuration inconsistency introduced with the coherent
memory area for QEMU virt with pager enabled.

Fixes: 5402a9fe46f9 ("qemu_virt: enable smp boot")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: juno: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0x180000000 for Juno.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wik

plat-vexpress: juno: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0x180000000 for Juno.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: fvp: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0xa00000000 for FVP.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wi

plat-vexpress: fvp: add missing DRAM1

Defines missing DRAM1 base 0x880000000 size 0xa00000000 for FVP.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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