plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size rel

plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size relative
to DRAM0_BASE.

Signed-off-by: Wen Bin <a1231512a@163.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-hikey: make DRAM1_BASE configurable

This commit introduces the CFG_DRAM1_BASE configuration switch
in the plat-hikey platform.

Signed-off-by: Wen Bin <a1231512a@163.com>
Acked-by: Etienne Carr

plat-hikey: make DRAM1_BASE configurable

This commit introduces the CFG_DRAM1_BASE configuration switch
in the plat-hikey platform.

Signed-off-by: Wen Bin <a1231512a@163.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey960: add support for 6G boards (CFG_DRAM_SIZE_GB=6)

Adds support for CFG_DRAM_SIZE_GB=6 and declares the non-secure
physical memory range 4~7G which may be used as shared memory by Linux
[1].

hikey960: add support for 6G boards (CFG_DRAM_SIZE_GB=6)

Adds support for CFG_DRAM_SIZE_GB=6 and declares the non-secure
physical memory range 4~7G which may be used as shared memory by Linux
[1].

Link: [1] https://github.com/96boards-hikey/OpenPlatformPkg/blob/50c813d0b9b3/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c#L40-L42
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey960: fix memory mapping for 4G boards (CFG_DRAM_SIZE_GB=4)

HiKey960 boards equipped with 4G of RAM may use physical addresses in
the range 8G~8.5G [1]. This range is currently not declared in O

hikey960: fix memory mapping for 4G boards (CFG_DRAM_SIZE_GB=4)

HiKey960 boards equipped with 4G of RAM may use physical addresses in
the range 8G~8.5G [1]. This range is currently not declared in OP-TEE,
so if Linux happens to be using it for shared memory, it will cause
problems. This can happen when:
1. Dynamic shared memory is enabled in OP-TEE (CFG_CORE_DYN_SHM=y) and
used by the kernel driver ("optee: dynamic shared memory is enabled" in
the boot log), and
2. The UEFI firmware is recent enough to report the whole physical
address range to the kernel (introduced in edk2's OpenPlatformPkg
commit 50c813d0b9b3 ("Platforms/HiKey960: Support 4G or more memory
space for RAM") [2].

The typical error is (the address could be any value >4G):

E/TC:6 0 tee_entry_std:551 Bad arg address 0x217e9a000

This commit fixes the issue by adding the missing memory range.
Obviously, dealing with PAs greater than 4G requires a 64-bit TEE core
or CFG_CORE_LARGE_PHYSICAL_ADDR=y, so a compile-time check is added.

Link: [1] https://github.com/96boards-hikey/OpenPlatformPkg/blob/50c813d0b9b3/Platforms/Hisilicon/HiKey960/Library/HiKey960Lib/HiKey960Mem.c#L34-L38
Link: [2] https://github.com/96boards-hikey/OpenPlatformPkg/commit/50c813d0b9b3
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Sungjin Park <sungjinp@gmail.com>

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hikey: Add support for UART2

UART2 is console interface provided on the 40-pin Low Speed
Connector in addition to the default UART3.

Reviewed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-b

hikey: Add support for UART2

UART2 is console interface provided on the 40-pin Low Speed
Connector in addition to the default UART3.

Reviewed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>

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hikey960: change DRAM1_SIZE_NSEC for 4GB board

SoC reference manual [1] page 2-23 says that the DRAM address range is
0x00000000 - 0xDFFFFFFF for a total of 3.5GB, so the limit would seem
to be 0xE0

hikey960: change DRAM1_SIZE_NSEC for 4GB board

SoC reference manual [1] page 2-23 says that the DRAM address range is
0x00000000 - 0xDFFFFFFF for a total of 3.5GB, so the limit would seem
to be 0xE0000000, not 0x100000000, or 0xFFE00000 based on [2] and [3].

Link: [1] https://github.com/96boards/documentation/raw/master/consumer/hikey/hikey960/hardware-docs/HiKey960_SoC_Reference_Manual.pdf
Link: [2] https://github.com/OP-TEE/optee_os/issues/2597#issuecomment-428587050
Link: [3] https://github.com/OP-TEE/optee_os/issues/2597#issuecomment-428865951
Fixes: https://github.com/OP-TEE/optee_os/issues/2597
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-hikey: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <eti

plat-hikey: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)

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core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ confi

core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ configuration directives as
NB_CORE was the last remaining one.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura

core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config

core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c

core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: register additional dyn shm

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

hikey: fix typo

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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hikey, hikey960: enable dynamic shared memory

Enables dynamic shared memory by registering the non-secure memory
range in plat-hikey/main.c.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro

hikey, hikey960: enable dynamic shared memory

Enables dynamic shared memory by registering the non-secure memory
range in plat-hikey/main.c.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-hikey: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-hikey platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander

core: plat-hikey: increase CFG_TEE_RAM_VA_SIZE

Increases CFG_TEE_RAM_VA_SIZE to 2 MiB for the plat-hikey platform.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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hikey: Set default value for CONSOLE_UART_BASE in conf.mk

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB

hikey: add support for hikey960

The HiKey 960 development platform is based around the Huawei Kirin 960
octa-core ARM big.LITTLE processor with four ARM Cortex-A73 and four
Cortex-A53 cores with 3GB of LPDDR4 SDRAM memory, 32GB of UFS 2.0 flash
storage, and the latest generation Mali G71 MP8 graphics processor.

See https://www.96boards.org/product/hikey960 for more details.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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hikey: use defines for pl011 uart base addresses

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

plat-hikey: enable 64-bit paging

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-hikey: configure and enable Secure Data Path by default

Reserve 4 MiB (0x3E800000 - 0x3EC00000) from the lower part of the DRAM
area that is already reserved for OP-TEE by UEFI (0x3E000000 -
0x

plat-hikey: configure and enable Secure Data Path by default

Reserve 4 MiB (0x3E800000 - 0x3EC00000) from the lower part of the DRAM
area that is already reserved for OP-TEE by UEFI (0x3E000000 -
0x40000000) to serve as the Secure Data Path pool.

A 2 MiB space is left between the top of this area and the NW/SW shared
memory, because we need the SDP area to be 4 MiB-aligned in order to
be protected by the memory firewall (protection is handled by ARM
Trusted Firmware [4] and is not strictly required for SDP to work).

To use SDP with Linux on HiKey, you need a modified ION driver [1]
which is available in the Linaro repository [2], and the following
configuration [3]:

CONFIG_STAGING=y
CONFIG_ION=y
CONFIG_ION_DUMMY=y
CONFIG_ION_DUMMY_UNMAPPED_HEAP=y
CONFIG_ION_DUMMY_UNMAPPED_BASE=0x3e800000
CONFIG_ION_DUMMY_UNMAPPED_SIZE=0x00400000
CONFIG_ANDROID=y
CONFIG_ANDROID_TIMED_OUTPUT=n
CONFIG_ANDROID_LOW_MEMORY_KILLER=n

[1] https://github.com/linaro-swg/linux/compare/e31dd54997^...961993fde6
[2] https://github.com/linaro-swg/linux/tree/optee
[3] https://github.com/OP-TEE/build/pull/145
[4] https://github.com/96boards-hikey/arm-trusted-firmware/pull/13

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-hikey: update the memory layout description

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens

plat-hikey: update the memory layout description

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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