zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Er

zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-zynqmp: fixes interrupt controller

Updates GICC_OFFSET to account for the already-offset GIC_BASE.
Additionally initializes the interrupt controller with a pointer
to the interrupt chip.

Signe

plat-zynqmp: fixes interrupt controller

Updates GICC_OFFSET to account for the already-offset GIC_BASE.
Additionally initializes the interrupt controller with a pointer
to the interrupt chip.

Signed-off-by: Zachary Clark <zach.clark@dornerworks.com>
Reviewed-by: Ricardo Salveti <ricardo@foundries.io>

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plat-zynqmp: add ZCU104 and ZCU106 flavour support

Adding support for the ZCU104 and ZCU106 boards
since they possess the same core as the ZCU102.
This is to avoid having the "flavour not supported

plat-zynqmp: add ZCU104 and ZCU106 flavour support

Adding support for the ZCU104 and ZCU106 boards
since they possess the same core as the ZCU102.
This is to avoid having the "flavour not supported error"
when compiling for the ZCU104 and ZCU106.

Tested successfully on the ZCU106

Tested-by: Nasreddine Ouldei Tebina <tebina1@live.fr>
Signed-off-by: Nasreddine Ouldei Tebina <tebina1@live.fr>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>

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zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Foris

zynqmp: platform: provide uart configuration during compilation

Add possibility to provide UART configuration as a compile
flag (CFG_UART_BASE, CFG_UART_IT, CFG_UART_CLK_HZ).

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_D

zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_DDR_SIZE.

Automatic configuration of DDR memory mappings can also be done by device
tree (CFG_DT=y) and by overriding if necessary memory address for device
tree (CFG_DT_ADDR).

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: define the STACK_ALIGNMENT in terms of CACHELINE

Explicitily define the cache line length

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carrier

zynqmp: define the STACK_ALIGNMENT in terms of CACHELINE

Explicitily define the cache line length

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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zynqmp: add base address definitions

Add the base address definitions for the CSU and the CSUDMA modules

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Vesa Jääskeläinen <vesa

zynqmp: add base address definitions

Add the base address definitions for the CSU and the CSUDMA modules

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: zynqmp: use generic_ram_layout for defining dram layout

Switch to the generic generic_ram_layout header file for defining the
default dram layout. This allow allows the user to easily customiz

plat: zynqmp: use generic_ram_layout for defining dram layout

Switch to the generic generic_ram_layout header file for defining the
default dram layout. This allow allows the user to easily customize the
default dram base and size via CFG_TZDRAM_START/CFG_TZDRAM_SIZE.

Default values are still the same as previously set by platform_config.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: fix UART1 base for zcu102, zc1751_dc1, zc1751_dc2 flavors

Fix UART1 base address for zcu102, zc1751_dc1, zc1751_dc2 flavors.
More information provided p226 of UG1085 [1].

Link: [1] https://

zynqmp: fix UART1 base for zcu102, zc1751_dc1, zc1751_dc2 flavors

Fix UART1 base address for zcu102, zc1751_dc1, zc1751_dc2 flavors.
More information provided p226 of UG1085 [1].

Link: [1] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
Signed-off-by: Michael Grand <michael.grand.mg@gmail.com>
[jf: move URL to a Link: tag]
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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Add support for ultra96 ZynqMP board

Add flavor 'ultra96' to platform 'zynqmp'.
Redirect TEE console output to UART1.

Signed-off-by: Michael Grand <michael.grand.mg@gmail.com>
Acked-by: Jerome Fori

Add support for ultra96 ZynqMP board

Add flavor 'ultra96' to platform 'zynqmp'.
Redirect TEE console output to UART1.

Signed-off-by: Michael Grand <michael.grand.mg@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP

core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity

Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.

This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().

In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ confi

core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ configuration directives as
NB_CORE was the last remaining one.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to ov

core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR

TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configura

core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be config

core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be c

core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE

Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.

This change renames these macros so that they do not mess with the
platform configuration directives.

Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecate

core: deprecate DEVICEx_TYPE/_PA_BASE/_SIZE

Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecated since platform should use the more flexible
register_phys_mem() macro.

This change removes all occurrences of DEVICEx_TYPE/_PA_BASE/_SIZE
and use the register_phys_mem() instead.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most

core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most of the previous values at 24 kB or just above.

Platforms with a previous heap size defined larger than 64 kB overrides
the mk/config.mk setting with a $(platform-dir)/conf.mk setting using the
previous value.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey pager)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Aarch32 pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the gener

Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the generation of conf.h.

As a result, the definition of numerical flavor identifiers in the
multiple platform_config.h files is not needed anymore, and we can also
get rid of the PLATFORM_FLAVOR_IS() test macro. Instead, replace all
occurrences of '#if PLATFORM_FLAVOR_IS(foo)' with
'#if defined(PLATFORM_FLAVOR_foo)'.

This makes it possible to test the platform and not only the flavor in
any source file, so drop the manual definition of PLATFORM_hikey.

Finally, remove the definitions of platform_$(PLATFORM) and
platform_flavor_$(PLATFORM_FLAVOR) from core/core.mk since they are not
used.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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zynqmp: Map UART memory area as secure

Commit 1e00aeb97ffa ("core: non-linear mapping of secure world devices")
revealed a bug in the ZynqMP platform that mapped the UART non-secure
but looked up it

zynqmp: Map UART memory area as secure

Commit 1e00aeb97ffa ("core: non-linear mapping of secure world devices")
revealed a bug in the ZynqMP platform that mapped the UART non-secure
but looked up its VA as secure memory, resulting in an exception when
accessing the UART registers.
Fixing this by mapping the UART secure, making the mapping consistent
with the VA lookup.

Fixes: dc57f5a0e8f3 ("Add support for ZynqMP")
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add support for ZynqMP

Add support for Xilinx UltraScale+ Zynq MPSoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jero

Add support for ZynqMP

Add support for Xilinx UltraScale+ Zynq MPSoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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