1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2014, Linaro Limited 4 */ 5 6 #ifndef PLATFORM_CONFIG_H 7 #define PLATFORM_CONFIG_H 8 9 #include <mm/generic_ram_layout.h> 10 #include <stdint.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 #if defined(PLATFORM_FLAVOR_fvp) 16 17 #define GIC_BASE 0x2c000000 18 #define UART0_BASE 0x1c090000 19 #define UART1_BASE 0x1c0a0000 20 #define UART2_BASE 0x1c0b0000 21 #define UART3_BASE 0x1c0c0000 22 #define TZC400_BASE 0x2a4a0000 23 24 #define IT_UART1 38 25 26 #define CONSOLE_UART_BASE UART1_BASE 27 #define IT_CONSOLE_UART IT_UART1 28 29 #elif defined(PLATFORM_FLAVOR_juno) 30 31 #define GIC_BASE 0x2c010000 32 33 /* FPGA UART0 */ 34 #define UART0_BASE 0x1c090000 35 /* FPGA UART1 */ 36 #define UART1_BASE 0x1c0a0000 37 /* SoC UART0 */ 38 #define UART2_BASE 0x7ff80000 39 /* SoC UART1 */ 40 #define UART3_BASE 0x7ff70000 41 42 43 #define UART0_CLK_IN_HZ 24000000 44 #define UART1_CLK_IN_HZ 24000000 45 #define UART2_CLK_IN_HZ 7273800 46 #define UART3_CLK_IN_HZ 7273800 47 48 49 #define IT_UART3 116 50 51 #define CONSOLE_UART_BASE UART3_BASE 52 #define IT_CONSOLE_UART IT_UART3 53 #define CONSOLE_UART_CLK_IN_HZ UART3_CLK_IN_HZ 54 55 #elif defined(PLATFORM_FLAVOR_qemu_virt) 56 57 #define GIC_BASE 0x08000000 58 #define UART0_BASE 0x09000000 59 #define UART1_BASE 0x09040000 60 #define PCSC_BASE 0x09100000 61 62 #define IT_UART1 40 63 #define IT_PCSC 37 64 65 #define CONSOLE_UART_BASE UART1_BASE 66 #define IT_CONSOLE_UART IT_UART1 67 68 #elif defined(PLATFORM_FLAVOR_qemu_armv8a) 69 70 #define GIC_BASE 0x08000000 71 #define UART0_BASE 0x09000000 72 #define UART1_BASE 0x09040000 73 74 #define IT_UART1 40 75 #if defined(CFG_CORE_SEL2_SPMC) 76 #define IT_SEC_PHY_TIMER 3 77 #else 78 #define IT_SEC_PHY_TIMER 29 79 #endif 80 81 #define CONSOLE_UART_BASE UART1_BASE 82 #define IT_CONSOLE_UART IT_UART1 83 84 #elif defined(PLATFORM_FLAVOR_qemu_sbsa) 85 #define GIC_BASE 0x40060000 86 #define SECURE_UART_BASE 0x60030000 87 #define IT_SECURE_UART 40 88 89 #define CONSOLE_UART_BASE SECURE_UART_BASE 90 #define IT_CONSOLE_UART IT_SECURE_UART 91 #else 92 #error "Unknown platform flavor" 93 #endif 94 95 #if defined(PLATFORM_FLAVOR_fvp) 96 /* 97 * FVP specifics. 98 */ 99 100 #define DRAM0_BASE 0x80000000 101 #define DRAM0_SIZE 0x7f000000 102 103 #define DRAM1_BASE 0x880000000UL 104 #define DRAM1_SIZE 0x180000000UL 105 106 #define TZCDRAM_BASE 0xff000000 107 #define TZCDRAM_SIZE 0x01000000 108 109 #define GICC_OFFSET 0x0 110 #define GICD_OFFSET 0x3000000 111 #ifdef CFG_ARM_GICV3 112 #define GIC_REDIST_BASE 0x2F100000 113 #define GIC_REDIST_SIZE 0x00100000 114 #endif 115 116 #elif defined(PLATFORM_FLAVOR_juno) 117 /* 118 * Juno specifics. 119 */ 120 121 #define DRAM0_BASE 0x80000000 122 #define DRAM0_SIZE 0x7F000000 123 124 #define DRAM1_BASE 0x880000000UL 125 #define DRAM1_SIZE 0x180000000UL 126 127 #define GICC_OFFSET 0x1f000 128 #define GICD_OFFSET 0 129 130 #elif defined(PLATFORM_FLAVOR_qemu_virt) 131 /* 132 * QEMU virt specifics. 133 */ 134 135 #define SECRAM_BASE 0x0e000000 136 #define SECRAM_COHERENT_SIZE 4096 137 138 #define GICD_OFFSET 0 139 #define GICC_OFFSET 0x10000 140 141 #elif defined(PLATFORM_FLAVOR_qemu_armv8a) 142 143 #define GICD_OFFSET 0 144 #define GICC_OFFSET 0x10000 145 #ifdef CFG_ARM_GICV3 146 #define GIC_REDIST_BASE 0x080A0000 147 #define GIC_REDIST_SIZE 0x00F60000 148 #endif 149 150 #elif defined(PLATFORM_FLAVOR_qemu_sbsa) 151 #define GICD_OFFSET 0 152 #define GICC_OFFSET 0x10000 153 #define GIC_REDIST_BASE 0x40080000 154 #define GIC_REDIST_SIZE 0x04000000 155 #else 156 #error "Unknown platform flavor" 157 #endif 158 159 #define GICD_BASE (GIC_BASE + GICD_OFFSET) 160 #define GICC_BASE (GIC_BASE + GICC_OFFSET) 161 162 #ifndef UART_BAUDRATE 163 #define UART_BAUDRATE 115200 164 #endif 165 #ifndef CONSOLE_BAUDRATE 166 #define CONSOLE_BAUDRATE UART_BAUDRATE 167 #endif 168 169 /* For virtual platforms where there isn't a clock */ 170 #ifndef CONSOLE_UART_CLK_IN_HZ 171 #define CONSOLE_UART_CLK_IN_HZ 1 172 #endif 173 174 #endif /*PLATFORM_CONFIG_H*/ 175