| #
55ab8f06 |
| 27-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let console_init() be common code to have a chance to initialize those console
core: Refactor console_init() and introduce plat_console_init()
Since there are some cross-platform console drivers, we let console_init() be common code to have a chance to initialize those console drivers (e.g., semihosting console).
If the cross-platform console drivers are not configured to be compiled, plat_console_init() will be invoked to initialize platform-specific console driver.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
e708156a |
| 09-Aug-2023 |
Sriram Sriram <sriramsriram@microsoft.com> |
core: arm: plat-versal: Add maybe_unused attribute to constant strings
If log level is set to print only EMSGs, constant strings can be unused. Add maybe_unused attribute to prevent compilation erro
core: arm: plat-versal: Add maybe_unused attribute to constant strings
If log level is set to print only EMSGs, constant strings can be unused. Add maybe_unused attribute to prevent compilation errors.
Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| #
df913c6d |
| 02-Aug-2023 |
Alvin Chang <alvinga@andestech.com> |
core: arm: Rename primary_init_intc() to boot_primary_init_intc()
Since interrupt controllers are usually initialized in boot stage, rename primary_init_intc() to boot_primary_init_intc().
Signed-o
core: arm: Rename primary_init_intc() to boot_primary_init_intc()
Since interrupt controllers are usually initialized in boot stage, rename primary_init_intc() to boot_primary_init_intc().
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| #
ef50391e |
| 19-Jul-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: rename interrupt controller functions
This commit renames interrupt controller function names to be more generic: - Rename main_init_gic() to primary_init_intc() - Rename secondary_init_gic()
core: rename interrupt controller functions
This commit renames interrupt controller function names to be more generic: - Rename main_init_gic() to primary_init_intc() - Rename secondary_init_gic() to secondary_init_intc()
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| #
0ee3f52e |
| 16-May-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: gic: factorize call to gic_init() or gic_init_base_addr()
Platforms call either gic_init() or gic_init_base_addr() depending on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This chang
drivers: gic: factorize call to gic_init() or gic_init_base_addr()
Platforms call either gic_init() or gic_init_base_addr() depending on whether CFG_WITH_ARM_TRUSTED_FW is defined or not. This change factorize this logic from gic_init() implementation and makes gic_init_base_addr() local to gic.c.
For that purpose functions gic_init_base_address() and gic_dt_get_irq() are moved inside gic.c source file. source file.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
67e55c51 |
| 16-May-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: define main interrupt controller data from its driver
All but one platforms define CPU core interrupt controller from their platform main.c source file next to its main interrupt handler. This
core: define main interrupt controller data from its driver
All but one platforms define CPU core interrupt controller from their platform main.c source file next to its main interrupt handler. This change factorize these implementation by moving the definition of the controller data instance straight in the controller driver source file. This change makes each controller driver to implement straight itr_core_handler() function, preventing a extra branch on interrupt execution. Interrupt controller driver initialization function now straight calls itr_core_init().
This changes treats case when CFG_CORE_WORKAROUND_ARM_NMFI is enable to not conflict with core/arch/arm/kernel/thread.c that already overrides itr_core_handler() weak implementation.
With this change, the main controller initialization function (gic_init(), gic_init_base_addr(), gic_cpu_init() and hfic_init()) no more gets the controller data as input argument.
As a consequence, definition of struct hfic_data and struct gic_data moves from their respective driver header file to the respective driver source file.
As a consequence, gic_dump() no more requires an argument.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
17d6dc51 |
| 03-Jan-2023 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
plat-versal: program the FPGA during OP-TEE initialization
Users can program the FPGA image by placing it at CFG_VERSAL_FPGA_DDR_ADDR.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-
plat-versal: program the FPGA during OP-TEE initialization
Users can program the FPGA image by placing it at CFG_VERSAL_FPGA_DDR_ADDR.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
a51510ce |
| 03-Jan-2023 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
plat-versal: allow RPMB init only on secured boards
Allow writing the RPMB key only on secured boards.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.for
plat-versal: allow RPMB init only on secured boards
Allow writing the RPMB key only on secured boards.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
09fe420b |
| 03-Jan-2023 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
plat-versal: print platform information
Output platform information banner to the console. This includes SoC version and the state of the hardware root of trust configuration.
Signed-off-by: Jorge
plat-versal: print platform information
Output platform information banner to the console. This includes SoC version and the state of the hardware root of trust configuration.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| #
2ac8d9a8 |
| 06-Apr-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
plat-versal: add support for Xilinx's Versal ACAP platform
Initial support for the Versal ACAP validated on the AI Core Series VKC190 Evaluation Kit.
The following BIF file is used by bootgen to ge
plat-versal: add support for Xilinx's Versal ACAP platform
Initial support for the Versal ACAP validated on the AI Core Series VKC190 Evaluation Kit.
The following BIF file is used by bootgen to generate the Versal boot.bin image.
the_ROM_image: { image { { type=bootimage, file=vpl_gen_fixed.pdi } { type=bootloader, file=plm.elf } { core=psm, file=psmfw.elf } }
image { id = 0x1c000000, name=apu_subsystem { type=raw, load=0x00001000, file=system.dtb } { core=a72-0, exception_level=el-3, trustzone, file=bl31.elf } { core=a72-0, exception_level=el-2, file=u-boot.elf } { core=a72-0, exception_level=el-1, trustzone, file=tee.elf } } }
$ ./bootgen -arch versal -image boot.bif -o BOOT.BIN
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: John Linn <linnj@xilinx.com> Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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