Home
last modified time | relevance | path

Searched +full:spi +full:- +full:rx +full:- +full:bus +full:- +full:width (Results 1 – 25 of 460) sorted by relevance

12345678910>>...19

/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
[all …]
H A Dspi-bus.txt1 SPI (Serial Peripheral Interface) busses
3 SPI busses can be described with a node for the SPI master device
4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
6 SPI master mode. This binding does not describe SPI controllers
9 The SPI master node requires the following properties:
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: "spi-controller.yaml#"
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]
H A Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
[all …]
H A Dallwinner,sun6i-a31-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
H A Dallwinner,sun4i-a10-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
23 i2c-switch@77 {
26 #address-cells = <1>;
27 #size-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 shunt-resistor = <1000>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 mmc-hs200-1_8v;
19 #address-cells = <2>;
20 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "cfi-flash";
30 bank-width = <2>;
31 device-width = <1>;
35 compatible = "fsl,ifc-nand";
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
21 stdout-path = "serial0:115200n8";
24 sb_3v3: regulator-sb3v3 {
25 compatible = "regulator-fixed";
26 regulator-name = "MC34717-3.3VSB";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
H A Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 stdout-path = "serial0:115200n8";
39 mmc-hs200-1_8v;
40 sd-uhs-sdr104;
41 sd-uhs-sdr50;
42 sd-uhs-sdr25;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dnxp-spifi.txt1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
10 - compatible : Should be "nxp,lpc1773-spifi"
11 - reg : the first contains the register location and length,
13 - reg-names: Should contain the reg names "spifi" and "flash"
14 - interrupts : Should contain the interrupt for the device
15 - clocks : The clocks needed by the SPIFI controller
16 - clock-names : Should contain the clock names "spifi" and "reg"
19 - resets : phandle + reset specifier
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1106-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
14 stdout-path = &uart2;
15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
18 secure-otp@ff3fd8000 {
19 compatible = "rockchip,rv1106-secure-otp";
24 u-boot,dm-spl;
30 mmc-ecsd = <0x3F000>;
31 bus-width = <8>;
32 mmc-hs200-1_8v;
33 u-boot,dm-spl;
[all …]
H A Drk1808-u-boot.dtsi1 // SPDX-License-Identifier: GPL-2.0+
23 stdout-path = &uart2;
24 u-boot,spl-boot-order = &spi_nand, &spi_nor, &emmc;
30 u-boot,dm-pre-reloc;
35 u-boot,dm-spl;
39 u-boot,dm-spl;
43 u-boot,dm-spl;
47 u-boot,dm-spl;
51 u-boot,dm-spl;
55 u-boot,dm-spl;
[all …]
H A Drk3528-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
14 stdout-path = &uart2;
15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
18 secure-otp@ffcd0000 {
19 compatible = "rockchip,rk3528-secure-otp";
24 u-boot,dm-spl;
31 u-boot,dm-spl;
36 u-boot,dm-spl;
41 /delete-property/ assigned-clocks;
42 /delete-property/ assigned-clock-rates;
[all …]
H A Drk3562-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
14 stdout-path = &uart2;
15 u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
18 secure-otp@ff920000 {
19 compatible = "rockchip,rk3562-secure-otp";
24 u-boot,dm-spl;
30 u-boot,dm-spl;
35 u-boot,dm-spl;
40 u-boot,dm-spl;
45 u-boot,dm-pre-reloc;
[all …]
H A Drk3588-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart2;
17 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
20 secure-otp@fe3a0000 {
21 u-boot,dm-spl;
22 compatible = "rockchip,rk3588-secure-otp";
28 u-boot,dm-spl;
32 u-boot,dm-spl;
36 u-boot,dm-pre-reloc;
[all …]
H A Dpx30-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
14 u-boot,spl-boot-order = &emmc, &sdmmc;
15 stdout-path = &uart2;
18 secure-otp@ff110000 {
19 compatible = "rockchip,px30-secure-otp";
27 u-boot,dm-pre-reloc;
31 u-boot,dm-pre-reloc;
35 clock-frequency = <24000000>;
36 u-boot,dm-pre-reloc;
40 clock-frequency = <24000000>;
[all …]
H A Drk3308-u-boot.dtsi4 * SPDX-License-Identifier: GPL-2.0+
14 stdout-path = &uart2;
15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
18 secure-otp@ff2a8000 {
19 compatible = "rockchip,rk3308-secure-otp";
23 u-boot,dm-pre-reloc;
28 u-boot,dm-pre-reloc;
33 u-boot,dm-pre-reloc;
37 u-boot,dm-pre-reloc;
41 u-boot,dm-pre-reloc;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dimx6sx-sdb.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
12 clock-frequency = <100000>;
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_i2c1>;
23 regulator-min-microvolt = <300000>;
24 regulator-max-microvolt = <1875000>;
25 regulator-boot-on;
26 regulator-always-on;
27 regulator-ramp-delay = <6250>;
[all …]
H A Dimx6sx-sdb-reva.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
9 compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx";
13 clock-frequency = <100000>;
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinctrl_i2c1>;
24 regulator-min-microvolt = <300000>;
25 regulator-max-microvolt = <1875000>;
26 regulator-boot-on;
27 regulator-always-on;
[all …]
H A Datlas6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
[all …]
H A Drv1106g-38x38-ipc-v10-spi-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
9 #include "rv1106-evb.dtsi"
10 #include "rv1106-ipc.dtsi"
13 model = "Rockchip RV1106G IPC38 V10 SPI NAND Board";
14 compatible = "rockchip,rv1106g-38x38-ipc-v10-spi-nand", "rockchip,rv1106";
16 vcc3v3_sd: vcc3v3-sd {
17 compatible = "regulator-fixed";
19 regulator-name = "vcc3v3_sd";
20 regulator-min-microvolt = <3300000>;
[all …]
H A Dr8a7743-iwg20m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1M-20M Qseven SOM
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 regulator-boot-on;
35 clock-frequency = <20000000>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dspi-uclass.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <spi.h>
12 #include <dm/device-internal.h>
13 #include <dm/uclass-internal.h>
21 static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) in spi_set_speed_mode() argument
26 ops = spi_get_ops(bus); in spi_set_speed_mode()
27 if (ops->set_speed) in spi_set_speed_mode()
28 ret = ops->set_speed(bus, speed); in spi_set_speed_mode()
30 ret = -EINVAL; in spi_set_speed_mode()
36 if (ops->set_mode) in spi_set_speed_mode()
[all …]

12345678910>>...19