xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/px30-u-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	aliases {
9*4882a593Smuzhiyun		mmc0 = &emmc;
10*4882a593Smuzhiyun		mmc1 = &sdmmc;
11*4882a593Smuzhiyun	};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	chosen {
14*4882a593Smuzhiyun		u-boot,spl-boot-order = &emmc, &sdmmc;
15*4882a593Smuzhiyun		stdout-path = &uart2;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	secure-otp@ff110000 {
19*4882a593Smuzhiyun		compatible = "rockchip,px30-secure-otp";
20*4882a593Smuzhiyun		reg = <0x0 0xff110000 0x0 0x4000>;
21*4882a593Smuzhiyun		secure_conf = <0xff11C008>;
22*4882a593Smuzhiyun		mask_addr = <0xff2d0000>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun&psci {
27*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
28*4882a593Smuzhiyun};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun&dmc {
31*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
32*4882a593Smuzhiyun};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun&uart5 {
35*4882a593Smuzhiyun	clock-frequency = <24000000>;
36*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&uart2 {
40*4882a593Smuzhiyun	clock-frequency = <24000000>;
41*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
42*4882a593Smuzhiyun};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun&nandc0 {
45*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
46*4882a593Smuzhiyun	status = "okay";
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&sdmmc {
50*4882a593Smuzhiyun	u-boot,dm-spl;
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&emmc {
54*4882a593Smuzhiyun	u-boot,dm-spl;
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&pmugrf {
58*4882a593Smuzhiyun	u-boot,dm-spl;
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&cru {
62*4882a593Smuzhiyun	u-boot,dm-spl;
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&crypto {
66*4882a593Smuzhiyun	u-boot,dm-spl;
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&pmucru {
70*4882a593Smuzhiyun	u-boot,dm-spl;
71*4882a593Smuzhiyun};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun&saradc {
74*4882a593Smuzhiyun	u-boot,dm-spl;
75*4882a593Smuzhiyun	status = "okay";
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&gpio0 {
79*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
80*4882a593Smuzhiyun	status = "disabled";
81*4882a593Smuzhiyun};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun&gpio1 {
84*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
85*4882a593Smuzhiyun	status = "disabled";
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&gpio2 {
89*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
90*4882a593Smuzhiyun	status = "disabled";
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&gpio3 {
94*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
95*4882a593Smuzhiyun	status = "disabled";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&usb20_otg {
99*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&usb2phy_grf {
103*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
104*4882a593Smuzhiyun	status = "okay";
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&u2phy {
108*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun&u2phy_otg {
113*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
114*4882a593Smuzhiyun	status = "okay";
115*4882a593Smuzhiyun};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun&sfc {
118*4882a593Smuzhiyun	u-boot,dm-spl;
119*4882a593Smuzhiyun	/delete-property/ pinctrl-names;
120*4882a593Smuzhiyun	/delete-property/ pinctrl-0;
121*4882a593Smuzhiyun	/delete-property/ assigned-clocks;
122*4882a593Smuzhiyun	/delete-property/ assigned-clock-rates;
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	#address-cells = <1>;
126*4882a593Smuzhiyun	#size-cells = <0>;
127*4882a593Smuzhiyun	spi_nand: flash@0 {
128*4882a593Smuzhiyun		u-boot,dm-spl;
129*4882a593Smuzhiyun		compatible = "spi-nand";
130*4882a593Smuzhiyun		reg = <0>;
131*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
132*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
133*4882a593Smuzhiyun		spi-max-frequency = <75000000>;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	spi_nor: flash@1 {
137*4882a593Smuzhiyun		u-boot,dm-spl;
138*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
139*4882a593Smuzhiyun		label = "sfc_nor";
140*4882a593Smuzhiyun		reg = <0>;
141*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
142*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
143*4882a593Smuzhiyun		spi-max-frequency = <100000000>;
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun&nandc0 {
148*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
149*4882a593Smuzhiyun	status = "okay";
150*4882a593Smuzhiyun	#address-cells = <1>;
151*4882a593Smuzhiyun	#size-cells = <0>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	nand@0 {
154*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
155*4882a593Smuzhiyun		reg = <0>;
156*4882a593Smuzhiyun		nand-ecc-mode = "hw_syndrome";
157*4882a593Smuzhiyun		nand-ecc-strength = <16>;
158*4882a593Smuzhiyun		nand-ecc-step-size = <1024>;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun};
161