1*4882a593SmuzhiyunSTM32 QSPI controller device tree bindings 2*4882a593Smuzhiyun-------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : should be "st,stm32-qspi". 6*4882a593Smuzhiyun- reg : 1. Physical base address and size of SPI registers map. 7*4882a593Smuzhiyun 2. Physical base address & size of mapped NOR Flash. 8*4882a593Smuzhiyun- spi-max-frequency : Max supported spi frequency. 9*4882a593Smuzhiyun- status : enable in requried dts. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunConnected flash properties 12*4882a593Smuzhiyun-------------------------- 13*4882a593Smuzhiyun- spi-max-frequency : Max supported spi frequency. 14*4882a593Smuzhiyun- spi-tx-bus-width : Bus width (number of lines) for writing (1-4) 15*4882a593Smuzhiyun- spi-rx-bus-width : Bus width (number of lines) for reading (1-4) 16*4882a593Smuzhiyun- memory-map : Address and size for memory-mapping the flash 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun qspi: quadspi@A0001000 { 20*4882a593Smuzhiyun compatible = "st,stm32-qspi"; 21*4882a593Smuzhiyun #address-cells = <1>; 22*4882a593Smuzhiyun #size-cells = <0>; 23*4882a593Smuzhiyun reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; 24*4882a593Smuzhiyun reg-names = "QuadSPI", "QuadSPI-memory"; 25*4882a593Smuzhiyun interrupts = <92>; 26*4882a593Smuzhiyun spi-max-frequency = <108000000>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun qflash0: n25q128a { 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <1>; 32*4882a593Smuzhiyun compatible = "micron,n25q128a13", "spi-flash"; 33*4882a593Smuzhiyun spi-max-frequency = <108000000>; 34*4882a593Smuzhiyun spi-tx-bus-width = <4>; 35*4882a593Smuzhiyun spi-rx-bus-width = <4>; 36*4882a593Smuzhiyun memory-map = <0x90000000 0x1000000>; 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40