1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun aliases { 9*4882a593Smuzhiyun mmc0 = &emmc; 10*4882a593Smuzhiyun mmc1 = &sdmmc; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = &uart2; 15*4882a593Smuzhiyun u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun secure-otp@ff2a8000 { 19*4882a593Smuzhiyun compatible = "rockchip,rk3308-secure-otp"; 20*4882a593Smuzhiyun reg = <0x0 0xff2a8000 0x0 0x4000>; 21*4882a593Smuzhiyun secure_conf = <0xff2b0004>; 22*4882a593Smuzhiyun mask_addr = <0xff540000>; 23*4882a593Smuzhiyun u-boot,dm-pre-reloc; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&psci { 28*4882a593Smuzhiyun u-boot,dm-pre-reloc; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&dmc { 33*4882a593Smuzhiyun u-boot,dm-pre-reloc; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun&cru { 37*4882a593Smuzhiyun u-boot,dm-pre-reloc; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&emmc { 41*4882a593Smuzhiyun u-boot,dm-pre-reloc; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&grf { 45*4882a593Smuzhiyun u-boot,dm-pre-reloc; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&nandc { 49*4882a593Smuzhiyun u-boot,dm-pre-reloc; 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <0>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun nand@0 { 55*4882a593Smuzhiyun u-boot,dm-spl; 56*4882a593Smuzhiyun reg = <0>; 57*4882a593Smuzhiyun nand-ecc-mode = "hw"; 58*4882a593Smuzhiyun nand-ecc-strength = <16>; 59*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&pinctrl { 64*4882a593Smuzhiyun u-boot,dm-pre-reloc; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&pcfg_pull_none_4ma { 68*4882a593Smuzhiyun u-boot,dm-spl; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&pcfg_pull_up_4ma { 72*4882a593Smuzhiyun u-boot,dm-spl; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&sdmmc { 76*4882a593Smuzhiyun u-boot,dm-pre-reloc; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&sdmmc_pin { 80*4882a593Smuzhiyun u-boot,dm-spl; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&sdmmc_clk { 84*4882a593Smuzhiyun u-boot,dm-spl; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&sdmmc_cmd { 88*4882a593Smuzhiyun u-boot,dm-spl; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&sdmmc_bus4 { 92*4882a593Smuzhiyun u-boot,dm-spl; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&sdmmc_pwren { 96*4882a593Smuzhiyun u-boot,dm-spl; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&sfc { 100*4882a593Smuzhiyun u-boot,dm-pre-reloc; 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <0>; 105*4882a593Smuzhiyun spi_nand: flash@0 { 106*4882a593Smuzhiyun u-boot,dm-spl; 107*4882a593Smuzhiyun compatible = "spi-nand"; 108*4882a593Smuzhiyun reg = <0>; 109*4882a593Smuzhiyun spi-tx-bus-width = <1>; 110*4882a593Smuzhiyun spi-rx-bus-width = <4>; 111*4882a593Smuzhiyun spi-max-frequency = <96000000>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun spi_nor: flash@1 { 114*4882a593Smuzhiyun u-boot,dm-spl; 115*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 116*4882a593Smuzhiyun label = "sfc_nor"; 117*4882a593Smuzhiyun reg = <0>; 118*4882a593Smuzhiyun spi-tx-bus-width = <1>; 119*4882a593Smuzhiyun spi-rx-bus-width = <4>; 120*4882a593Smuzhiyun spi-max-frequency = <96000000>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun}; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun&crypto { 125*4882a593Smuzhiyun u-boot,dm-pre-reloc; 126*4882a593Smuzhiyun status = "okay"; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&saradc { 130*4882a593Smuzhiyun u-boot,dm-pre-reloc; 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&uart0 { 135*4882a593Smuzhiyun u-boot,dm-pre-reloc; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&uart1 { 139*4882a593Smuzhiyun u-boot,dm-pre-reloc; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&uart2 { 143*4882a593Smuzhiyun u-boot,dm-pre-reloc; 144*4882a593Smuzhiyun clock-frequency = <24000000>; 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&uart3 { 149*4882a593Smuzhiyun u-boot,dm-pre-reloc; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&uart4 { 153*4882a593Smuzhiyun u-boot,dm-pre-reloc; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&usb2phy_grf { 157*4882a593Smuzhiyun u-boot,dm-pre-reloc; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&u2phy { 161*4882a593Smuzhiyun u-boot,dm-pre-reloc; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&u2phy_otg { 166*4882a593Smuzhiyun u-boot,dm-pre-reloc; 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&usb20_otg { 171*4882a593Smuzhiyun u-boot,dm-pre-reloc; 172*4882a593Smuzhiyun status = "okay"; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&route_rgb { 176*4882a593Smuzhiyun status = "disabled"; 177*4882a593Smuzhiyun}; 178