1/* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 u-boot,spl-boot-order = &emmc, &sdmmc; 15 stdout-path = &uart2; 16 }; 17 18 secure-otp@ff110000 { 19 compatible = "rockchip,px30-secure-otp"; 20 reg = <0x0 0xff110000 0x0 0x4000>; 21 secure_conf = <0xff11C008>; 22 mask_addr = <0xff2d0000>; 23 }; 24}; 25 26&psci { 27 u-boot,dm-pre-reloc; 28}; 29 30&dmc { 31 u-boot,dm-pre-reloc; 32}; 33 34&uart5 { 35 clock-frequency = <24000000>; 36 u-boot,dm-pre-reloc; 37}; 38 39&uart2 { 40 clock-frequency = <24000000>; 41 u-boot,dm-pre-reloc; 42}; 43 44&nandc0 { 45 u-boot,dm-pre-reloc; 46 status = "okay"; 47}; 48 49&sdmmc { 50 u-boot,dm-spl; 51}; 52 53&emmc { 54 u-boot,dm-spl; 55}; 56 57&pmugrf { 58 u-boot,dm-spl; 59}; 60 61&cru { 62 u-boot,dm-spl; 63}; 64 65&crypto { 66 u-boot,dm-spl; 67}; 68 69&pmucru { 70 u-boot,dm-spl; 71}; 72 73&saradc { 74 u-boot,dm-spl; 75 status = "okay"; 76}; 77 78&gpio0 { 79 u-boot,dm-pre-reloc; 80 status = "disabled"; 81}; 82 83&gpio1 { 84 u-boot,dm-pre-reloc; 85 status = "disabled"; 86}; 87 88&gpio2 { 89 u-boot,dm-pre-reloc; 90 status = "disabled"; 91}; 92 93&gpio3 { 94 u-boot,dm-pre-reloc; 95 status = "disabled"; 96}; 97 98&usb20_otg { 99 u-boot,dm-pre-reloc; 100}; 101 102&usb2phy_grf { 103 u-boot,dm-pre-reloc; 104 status = "okay"; 105}; 106 107&u2phy { 108 u-boot,dm-pre-reloc; 109 status = "okay"; 110}; 111 112&u2phy_otg { 113 u-boot,dm-pre-reloc; 114 status = "okay"; 115}; 116 117&sfc { 118 u-boot,dm-spl; 119 /delete-property/ pinctrl-names; 120 /delete-property/ pinctrl-0; 121 /delete-property/ assigned-clocks; 122 /delete-property/ assigned-clock-rates; 123 status = "okay"; 124 125 #address-cells = <1>; 126 #size-cells = <0>; 127 spi_nand: flash@0 { 128 u-boot,dm-spl; 129 compatible = "spi-nand"; 130 reg = <0>; 131 spi-tx-bus-width = <1>; 132 spi-rx-bus-width = <4>; 133 spi-max-frequency = <75000000>; 134 }; 135 136 spi_nor: flash@1 { 137 u-boot,dm-spl; 138 compatible = "jedec,spi-nor"; 139 label = "sfc_nor"; 140 reg = <0>; 141 spi-tx-bus-width = <1>; 142 spi-rx-bus-width = <4>; 143 spi-max-frequency = <100000000>; 144 }; 145}; 146 147&nandc0 { 148 u-boot,dm-pre-reloc; 149 status = "okay"; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 nand@0 { 154 u-boot,dm-pre-reloc; 155 reg = <0>; 156 nand-ecc-mode = "hw_syndrome"; 157 nand-ecc-strength = <16>; 158 nand-ecc-step-size = <1024>; 159 }; 160}; 161