xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rk3562-u-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	aliases {
9*4882a593Smuzhiyun		mmc0 = &sdhci;
10*4882a593Smuzhiyun		mmc1 = &sdmmc0;
11*4882a593Smuzhiyun	};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	chosen {
14*4882a593Smuzhiyun		stdout-path = &uart2;
15*4882a593Smuzhiyun		u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	secure-otp@ff920000 {
19*4882a593Smuzhiyun		compatible = "rockchip,rk3562-secure-otp";
20*4882a593Smuzhiyun		reg = <0x0 0xff920000 0x0 0x4000>;
21*4882a593Smuzhiyun		secure_conf = <0xff020034>;
22*4882a593Smuzhiyun		mask_addr = <0x0>;
23*4882a593Smuzhiyun		cru_rst_addr = <0xff130438>;
24*4882a593Smuzhiyun		u-boot,dm-spl;
25*4882a593Smuzhiyun		status = "okay";
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun&sys_grf {
30*4882a593Smuzhiyun	u-boot,dm-spl;
31*4882a593Smuzhiyun	status = "okay";
32*4882a593Smuzhiyun};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun&ioc_grf {
35*4882a593Smuzhiyun	u-boot,dm-spl;
36*4882a593Smuzhiyun	status = "okay";
37*4882a593Smuzhiyun};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun&pmu_grf {
40*4882a593Smuzhiyun	u-boot,dm-spl;
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun&usbphy_grf {
45*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
46*4882a593Smuzhiyun	status = "okay";
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&firmware {
50*4882a593Smuzhiyun	u-boot,dm-spl;
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&scmi {
54*4882a593Smuzhiyun	u-boot,dm-spl;
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&scmi_clk {
58*4882a593Smuzhiyun	u-boot,dm-spl;
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&scmi_shmem {
62*4882a593Smuzhiyun	u-boot,dm-spl;
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&cru {
66*4882a593Smuzhiyun	u-boot,dm-spl;
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&crypto {
71*4882a593Smuzhiyun	u-boot,dm-spl;
72*4882a593Smuzhiyun	status = "okay";
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&rng {
76*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
77*4882a593Smuzhiyun	status = "okay";
78*4882a593Smuzhiyun};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun&uart2 {
81*4882a593Smuzhiyun	clock-frequency = <24000000>;
82*4882a593Smuzhiyun	u-boot,dm-spl;
83*4882a593Smuzhiyun	status = "okay";
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&saradc0 {
87*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
88*4882a593Smuzhiyun	status = "okay";
89*4882a593Smuzhiyun};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun&psci {
92*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
93*4882a593Smuzhiyun	status = "okay";
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&sdhci {
97*4882a593Smuzhiyun	bus-width = <8>;
98*4882a593Smuzhiyun	u-boot,dm-spl;
99*4882a593Smuzhiyun	/delete-property/ pinctrl-names;
100*4882a593Smuzhiyun	/delete-property/ pinctrl-0;
101*4882a593Smuzhiyun	mmc-hs400-1_8v;
102*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
103*4882a593Smuzhiyun	fixed-emmc-driver-type = <1>;
104*4882a593Smuzhiyun	status = "okay";
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&sdmmc0 {
108*4882a593Smuzhiyun	u-boot,dm-spl;
109*4882a593Smuzhiyun	pinctrl-names = "default";
110*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
111*4882a593Smuzhiyun	status = "okay";
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&sdmmc0_pins {
115*4882a593Smuzhiyun	u-boot,dm-spl;
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&sdmmc0_bus4 {
119*4882a593Smuzhiyun	u-boot,dm-spl;
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&sdmmc0_clk {
123*4882a593Smuzhiyun	u-boot,dm-spl;
124*4882a593Smuzhiyun};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&sdmmc0_cmd {
127*4882a593Smuzhiyun	u-boot,dm-spl;
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&sdmmc0_det {
131*4882a593Smuzhiyun	u-boot,dm-spl;
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&sfc {
135*4882a593Smuzhiyun	u-boot,dm-spl;
136*4882a593Smuzhiyun	status = "okay";
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	#address-cells = <1>;
139*4882a593Smuzhiyun	#size-cells = <0>;
140*4882a593Smuzhiyun	spi_nand: flash@0 {
141*4882a593Smuzhiyun		u-boot,dm-spl;
142*4882a593Smuzhiyun		compatible = "spi-nand";
143*4882a593Smuzhiyun		reg = <0>;
144*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
145*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
146*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	spi_nor: flash@1 {
150*4882a593Smuzhiyun		u-boot,dm-spl;
151*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
152*4882a593Smuzhiyun		label = "sfc_nor";
153*4882a593Smuzhiyun		reg = <0>;
154*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
155*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
156*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun&pinctrl {
161*4882a593Smuzhiyun	u-boot,dm-spl;
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&gpio0 {
166*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&gpio1 {
170*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun&gpio2 {
174*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&gpio3 {
178*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun&gpio4 {
182*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&pcfg_pull_up_drv_level_2 {
186*4882a593Smuzhiyun	u-boot,dm-spl;
187*4882a593Smuzhiyun	status = "okay";
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&pcfg_pull_up {
191*4882a593Smuzhiyun	u-boot,dm-spl;
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&u2phy {
196*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&u2phy_otg {
201*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
202*4882a593Smuzhiyun	status = "okay";
203*4882a593Smuzhiyun};
204