1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Freescale LS2080A QDS Board. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Copyright 2017 NXP 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun&esdhc { 13*4882a593Smuzhiyun mmc-hs200-1_8v; 14*4882a593Smuzhiyun status = "okay"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&ifc { 18*4882a593Smuzhiyun status = "okay"; 19*4882a593Smuzhiyun #address-cells = <2>; 20*4882a593Smuzhiyun #size-cells = <1>; 21*4882a593Smuzhiyun ranges = <0x0 0x0 0x5 0x80000000 0x08000000 22*4882a593Smuzhiyun 0x2 0x0 0x5 0x30000000 0x00010000 23*4882a593Smuzhiyun 0x3 0x0 0x5 0x20000000 0x00010000>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun nor@0,0 { 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <1>; 28*4882a593Smuzhiyun compatible = "cfi-flash"; 29*4882a593Smuzhiyun reg = <0x0 0x0 0x8000000>; 30*4882a593Smuzhiyun bank-width = <2>; 31*4882a593Smuzhiyun device-width = <1>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun nand@2,0 { 35*4882a593Smuzhiyun compatible = "fsl,ifc-nand"; 36*4882a593Smuzhiyun reg = <0x2 0x0 0x10000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpld@3,0 { 40*4882a593Smuzhiyun reg = <0x3 0x0 0x10000>; 41*4882a593Smuzhiyun compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&i2c0 { 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun pca9547@77 { 48*4882a593Smuzhiyun compatible = "nxp,pca9547"; 49*4882a593Smuzhiyun reg = <0x77>; 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <0>; 52*4882a593Smuzhiyun i2c@0 { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun reg = <0x00>; 56*4882a593Smuzhiyun rtc@68 { 57*4882a593Smuzhiyun compatible = "dallas,ds3232"; 58*4882a593Smuzhiyun reg = <0x68>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun i2c@2 { 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <0>; 65*4882a593Smuzhiyun reg = <0x02>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun ina220@40 { 68*4882a593Smuzhiyun compatible = "ti,ina220"; 69*4882a593Smuzhiyun reg = <0x40>; 70*4882a593Smuzhiyun shunt-resistor = <500>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun ina220@41 { 74*4882a593Smuzhiyun compatible = "ti,ina220"; 75*4882a593Smuzhiyun reg = <0x41>; 76*4882a593Smuzhiyun shunt-resistor = <1000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun i2c@3 { 81*4882a593Smuzhiyun #address-cells = <1>; 82*4882a593Smuzhiyun #size-cells = <0>; 83*4882a593Smuzhiyun reg = <0x3>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun adt7481@4c { 86*4882a593Smuzhiyun compatible = "adi,adt7461"; 87*4882a593Smuzhiyun reg = <0x4c>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&i2c1 { 94*4882a593Smuzhiyun status = "disabled"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&i2c2 { 98*4882a593Smuzhiyun status = "disabled"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&i2c3 { 102*4882a593Smuzhiyun status = "disabled"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&dspi { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun dflash0: n25q128a@0 { 108*4882a593Smuzhiyun #address-cells = <1>; 109*4882a593Smuzhiyun #size-cells = <1>; 110*4882a593Smuzhiyun compatible = "st,m25p80"; 111*4882a593Smuzhiyun spi-max-frequency = <3000000>; 112*4882a593Smuzhiyun reg = <0>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun dflash1: sst25wf040b@1 { 115*4882a593Smuzhiyun #address-cells = <1>; 116*4882a593Smuzhiyun #size-cells = <1>; 117*4882a593Smuzhiyun compatible = "st,m25p80"; 118*4882a593Smuzhiyun spi-max-frequency = <3000000>; 119*4882a593Smuzhiyun reg = <1>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun dflash2: en25s64@2 { 122*4882a593Smuzhiyun #address-cells = <1>; 123*4882a593Smuzhiyun #size-cells = <1>; 124*4882a593Smuzhiyun compatible = "st,m25p80"; 125*4882a593Smuzhiyun spi-max-frequency = <3000000>; 126*4882a593Smuzhiyun reg = <2>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&qspi { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun flash0: s25fl256s1@0 { 133*4882a593Smuzhiyun #address-cells = <1>; 134*4882a593Smuzhiyun #size-cells = <1>; 135*4882a593Smuzhiyun compatible = "st,m25p80"; 136*4882a593Smuzhiyun spi-max-frequency = <20000000>; 137*4882a593Smuzhiyun spi-rx-bus-width = <4>; 138*4882a593Smuzhiyun spi-tx-bus-width = <4>; 139*4882a593Smuzhiyun reg = <0>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun flash2: s25fl256s1@2 { 142*4882a593Smuzhiyun #address-cells = <1>; 143*4882a593Smuzhiyun #size-cells = <1>; 144*4882a593Smuzhiyun compatible = "st,m25p80"; 145*4882a593Smuzhiyun spi-max-frequency = <20000000>; 146*4882a593Smuzhiyun spi-rx-bus-width = <4>; 147*4882a593Smuzhiyun spi-tx-bus-width = <4>; 148*4882a593Smuzhiyun reg = <2>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&sata0 { 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&sata1 { 157*4882a593Smuzhiyun status = "okay"; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&usb0 { 161*4882a593Smuzhiyun status = "okay"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&usb1 { 165*4882a593Smuzhiyun status = "okay"; 166*4882a593Smuzhiyun}; 167