xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/spi-controller.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: SPI Controller Generic Binding
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Mark Brown <broonie@kernel.org>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  SPI busses can be described with a node for the SPI controller device
14*4882a593Smuzhiyun  and a set of child nodes for each SPI slave on the bus. The system SPI
15*4882a593Smuzhiyun  controller may be described for use in SPI master mode or in SPI slave mode,
16*4882a593Smuzhiyun  but not for both at the same time.
17*4882a593Smuzhiyun
18*4882a593Smuzhiyunproperties:
19*4882a593Smuzhiyun  $nodename:
20*4882a593Smuzhiyun    pattern: "^spi(@.*|-[0-9a-f])*$"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  "#address-cells":
23*4882a593Smuzhiyun    enum: [0, 1]
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  "#size-cells":
26*4882a593Smuzhiyun    const: 0
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  cs-gpios:
29*4882a593Smuzhiyun    description: |
30*4882a593Smuzhiyun      GPIOs used as chip selects.
31*4882a593Smuzhiyun      If that property is used, the number of chip selects will be
32*4882a593Smuzhiyun      increased automatically with max(cs-gpios, hardware chip selects).
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun      So if, for example, the controller has 4 CS lines, and the
35*4882a593Smuzhiyun      cs-gpios looks like this
36*4882a593Smuzhiyun        cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun      Then it should be configured so that num_chipselect = 4, with
39*4882a593Smuzhiyun      the following mapping
40*4882a593Smuzhiyun        cs0 : &gpio1 0 0
41*4882a593Smuzhiyun        cs1 : native
42*4882a593Smuzhiyun        cs2 : &gpio1 1 0
43*4882a593Smuzhiyun        cs3 : &gpio1 2 0
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun  num-cs:
46*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32
47*4882a593Smuzhiyun    description:
48*4882a593Smuzhiyun      Total number of chip selects.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  spi-slave:
51*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/flag
52*4882a593Smuzhiyun    description:
53*4882a593Smuzhiyun      The SPI controller acts as a slave, instead of a master.
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunallOf:
56*4882a593Smuzhiyun  - if:
57*4882a593Smuzhiyun      not:
58*4882a593Smuzhiyun        required:
59*4882a593Smuzhiyun          - spi-slave
60*4882a593Smuzhiyun    then:
61*4882a593Smuzhiyun      properties:
62*4882a593Smuzhiyun        "#address-cells":
63*4882a593Smuzhiyun          const: 1
64*4882a593Smuzhiyun    else:
65*4882a593Smuzhiyun      properties:
66*4882a593Smuzhiyun        "#address-cells":
67*4882a593Smuzhiyun          const: 0
68*4882a593Smuzhiyun
69*4882a593SmuzhiyunpatternProperties:
70*4882a593Smuzhiyun  "^slave$":
71*4882a593Smuzhiyun    type: object
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun    properties:
74*4882a593Smuzhiyun      compatible:
75*4882a593Smuzhiyun        description:
76*4882a593Smuzhiyun          Compatible of the SPI device.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun    required:
79*4882a593Smuzhiyun      - compatible
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun  "^.*@[0-9a-f]+$":
82*4882a593Smuzhiyun    type: object
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun    properties:
85*4882a593Smuzhiyun      compatible:
86*4882a593Smuzhiyun        description:
87*4882a593Smuzhiyun          Compatible of the SPI device.
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun      reg:
90*4882a593Smuzhiyun        minimum: 0
91*4882a593Smuzhiyun        maximum: 256
92*4882a593Smuzhiyun        description:
93*4882a593Smuzhiyun          Chip select used by the device.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun      spi-3wire:
96*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/flag
97*4882a593Smuzhiyun        description:
98*4882a593Smuzhiyun          The device requires 3-wire mode.
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun      spi-cpha:
101*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/flag
102*4882a593Smuzhiyun        description:
103*4882a593Smuzhiyun          The device requires shifted clock phase (CPHA) mode.
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun      spi-cpol:
106*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/flag
107*4882a593Smuzhiyun        description:
108*4882a593Smuzhiyun          The device requires inverse clock polarity (CPOL) mode.
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun      spi-cs-high:
111*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/flag
112*4882a593Smuzhiyun        description:
113*4882a593Smuzhiyun          The device requires the chip select active high.
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun      spi-lsb-first:
116*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/flag
117*4882a593Smuzhiyun        description:
118*4882a593Smuzhiyun          The device requires the LSB first mode.
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun      spi-max-frequency:
121*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
122*4882a593Smuzhiyun        description:
123*4882a593Smuzhiyun          Maximum SPI clocking speed of the device in Hz.
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun      spi-rx-bus-width:
126*4882a593Smuzhiyun        description:
127*4882a593Smuzhiyun          Bus width to the SPI bus used for read transfers.
128*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
129*4882a593Smuzhiyun        enum: [1, 2, 4, 8]
130*4882a593Smuzhiyun        default: 1
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun      spi-rx-delay-us:
133*4882a593Smuzhiyun        description:
134*4882a593Smuzhiyun          Delay, in microseconds, after a read transfer.
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun      spi-tx-bus-width:
137*4882a593Smuzhiyun        description:
138*4882a593Smuzhiyun          Bus width to the SPI bus used for write transfers.
139*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
140*4882a593Smuzhiyun        enum: [1, 2, 4, 8]
141*4882a593Smuzhiyun        default: 1
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun      spi-tx-delay-us:
144*4882a593Smuzhiyun        description:
145*4882a593Smuzhiyun          Delay, in microseconds, after a write transfer.
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun    required:
148*4882a593Smuzhiyun      - compatible
149*4882a593Smuzhiyun      - reg
150*4882a593Smuzhiyun
151*4882a593SmuzhiyunadditionalProperties: true
152*4882a593Smuzhiyun
153*4882a593Smuzhiyunexamples:
154*4882a593Smuzhiyun  - |
155*4882a593Smuzhiyun    spi@f00 {
156*4882a593Smuzhiyun        #address-cells = <1>;
157*4882a593Smuzhiyun        #size-cells = <0>;
158*4882a593Smuzhiyun        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
159*4882a593Smuzhiyun        reg = <0xf00 0x20>;
160*4882a593Smuzhiyun        interrupts = <2 13 0 2 14 0>;
161*4882a593Smuzhiyun        interrupt-parent = <&mpc5200_pic>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun        ethernet-switch@0 {
164*4882a593Smuzhiyun            compatible = "micrel,ks8995m";
165*4882a593Smuzhiyun            spi-max-frequency = <1000000>;
166*4882a593Smuzhiyun            reg = <0>;
167*4882a593Smuzhiyun        };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun        codec@1 {
170*4882a593Smuzhiyun            compatible = "ti,tlv320aic26";
171*4882a593Smuzhiyun            spi-max-frequency = <100000>;
172*4882a593Smuzhiyun            reg = <1>;
173*4882a593Smuzhiyun        };
174*4882a593Smuzhiyun    };
175