1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun aliases { 9*4882a593Smuzhiyun mmc0 = &sdhci; 10*4882a593Smuzhiyun mmc1 = &sdmmc; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun stdout-path = &uart2; 15*4882a593Smuzhiyun u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun secure-otp@ffcd0000 { 19*4882a593Smuzhiyun compatible = "rockchip,rk3528-secure-otp"; 20*4882a593Smuzhiyun reg = <0x0 0xffcd0000 0x0 0x4000>; 21*4882a593Smuzhiyun secure_conf = <0xff4500c0>; 22*4882a593Smuzhiyun mask_addr = <0x0>; 23*4882a593Smuzhiyun cru_rst_addr = <0xff4a8080>; 24*4882a593Smuzhiyun u-boot,dm-spl; 25*4882a593Smuzhiyun status = "okay"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&grf { 31*4882a593Smuzhiyun u-boot,dm-spl; 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&ioc_grf { 36*4882a593Smuzhiyun u-boot,dm-spl; 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&cru { 41*4882a593Smuzhiyun /delete-property/ assigned-clocks; 42*4882a593Smuzhiyun /delete-property/ assigned-clock-rates; 43*4882a593Smuzhiyun u-boot,dm-spl; 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&crypto { 48*4882a593Smuzhiyun u-boot,dm-spl; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&rng { 53*4882a593Smuzhiyun u-boot,dm-pre-reloc; 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&psci { 58*4882a593Smuzhiyun u-boot,dm-pre-reloc; 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&uart2 { 63*4882a593Smuzhiyun clock-frequency = <24000000>; 64*4882a593Smuzhiyun u-boot,dm-spl; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&sfc { 69*4882a593Smuzhiyun u-boot,dm-spl; 70*4882a593Smuzhiyun /delete-property/ pinctrl-names; 71*4882a593Smuzhiyun /delete-property/ pinctrl-0; 72*4882a593Smuzhiyun /delete-property/ assigned-clocks; 73*4882a593Smuzhiyun /delete-property/ assigned-clock-rates; 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #address-cells = <1>; 77*4882a593Smuzhiyun #size-cells = <0>; 78*4882a593Smuzhiyun spi_nand: flash@0 { 79*4882a593Smuzhiyun u-boot,dm-spl; 80*4882a593Smuzhiyun compatible = "spi-nand"; 81*4882a593Smuzhiyun reg = <0>; 82*4882a593Smuzhiyun spi-tx-bus-width = <1>; 83*4882a593Smuzhiyun spi-rx-bus-width = <4>; 84*4882a593Smuzhiyun spi-max-frequency = <75000000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun spi_nor: flash@1 { 88*4882a593Smuzhiyun u-boot,dm-spl; 89*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 90*4882a593Smuzhiyun label = "sfc_nor"; 91*4882a593Smuzhiyun reg = <0>; 92*4882a593Smuzhiyun spi-tx-bus-width = <1>; 93*4882a593Smuzhiyun spi-rx-bus-width = <4>; 94*4882a593Smuzhiyun spi-max-frequency = <100000000>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&sdhci { 99*4882a593Smuzhiyun bus-width = <8>; 100*4882a593Smuzhiyun u-boot,dm-spl; 101*4882a593Smuzhiyun /delete-property/ assigned-clocks; 102*4882a593Smuzhiyun /delete-property/ assigned-clock-rates; 103*4882a593Smuzhiyun /delete-property/ pinctrl-names; 104*4882a593Smuzhiyun /delete-property/ pinctrl-0; 105*4882a593Smuzhiyun mmc-hs400-1_8v; 106*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 107*4882a593Smuzhiyun fixed-emmc-driver-type = <1>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&sdmmc { 112*4882a593Smuzhiyun u-boot,dm-spl; 113*4882a593Smuzhiyun status = "okay"; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&saradc { 117*4882a593Smuzhiyun u-boot,dm-pre-reloc; 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&u2phy_otg { 122*4882a593Smuzhiyun u-boot,dm-pre-reloc; 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&usb2phy { 127*4882a593Smuzhiyun u-boot,dm-pre-reloc; 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&firmware { 132*4882a593Smuzhiyun u-boot,dm-spl; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&scmi { 136*4882a593Smuzhiyun u-boot,dm-spl; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&scmi_clk { 140*4882a593Smuzhiyun u-boot,dm-spl; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&scmi_shmem { 144*4882a593Smuzhiyun u-boot,dm-spl; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&pinctrl { 148*4882a593Smuzhiyun u-boot,dm-spl; 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&gpio0 { 153*4882a593Smuzhiyun u-boot,dm-spl; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&gpio1 { 157*4882a593Smuzhiyun u-boot,dm-spl; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&gpio2 { 161*4882a593Smuzhiyun u-boot,dm-spl; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&pcfg_pull_none_drv_level_1 { 165*4882a593Smuzhiyun u-boot,dm-spl; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&pcfg_pull_none_drv_level_2 { 169*4882a593Smuzhiyun u-boot,dm-spl; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&pcfg_pull_up_drv_level_1 { 173*4882a593Smuzhiyun u-boot,dm-spl; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&pcfg_pull_up_drv_level_2 { 177*4882a593Smuzhiyun u-boot,dm-spl; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun&pcfg_pull_up { 181*4882a593Smuzhiyun u-boot,dm-spl; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&pcfg_pull_none { 185*4882a593Smuzhiyun u-boot,dm-spl; 186*4882a593Smuzhiyun}; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun&sdmmc_pins { 189*4882a593Smuzhiyun u-boot,dm-spl; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&sdmmc_bus4 { 193*4882a593Smuzhiyun u-boot,dm-spl; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&sdmmc_clk { 197*4882a593Smuzhiyun u-boot,dm-spl; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&sdmmc_cmd { 201*4882a593Smuzhiyun u-boot,dm-spl; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&sdmmc_det { 205*4882a593Smuzhiyun u-boot,dm-spl; 206*4882a593Smuzhiyun}; 207