1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16 }; 17 18 secure-otp@ffcd0000 { 19 compatible = "rockchip,rk3528-secure-otp"; 20 reg = <0x0 0xffcd0000 0x0 0x4000>; 21 secure_conf = <0xff4500c0>; 22 mask_addr = <0x0>; 23 cru_rst_addr = <0xff4a8080>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27 28}; 29 30&grf { 31 u-boot,dm-spl; 32 status = "okay"; 33}; 34 35&ioc_grf { 36 u-boot,dm-spl; 37 status = "okay"; 38}; 39 40&cru { 41 /delete-property/ assigned-clocks; 42 /delete-property/ assigned-clock-rates; 43 u-boot,dm-spl; 44 status = "okay"; 45}; 46 47&crypto { 48 u-boot,dm-spl; 49 status = "okay"; 50}; 51 52&rng { 53 u-boot,dm-pre-reloc; 54 status = "okay"; 55}; 56 57&psci { 58 u-boot,dm-pre-reloc; 59 status = "okay"; 60}; 61 62&uart2 { 63 clock-frequency = <24000000>; 64 u-boot,dm-spl; 65 status = "okay"; 66}; 67 68&sfc { 69 u-boot,dm-spl; 70 /delete-property/ pinctrl-names; 71 /delete-property/ pinctrl-0; 72 /delete-property/ assigned-clocks; 73 /delete-property/ assigned-clock-rates; 74 status = "okay"; 75 76 #address-cells = <1>; 77 #size-cells = <0>; 78 spi_nand: flash@0 { 79 u-boot,dm-spl; 80 compatible = "spi-nand"; 81 reg = <0>; 82 spi-tx-bus-width = <1>; 83 spi-rx-bus-width = <4>; 84 spi-max-frequency = <75000000>; 85 }; 86 87 spi_nor: flash@1 { 88 u-boot,dm-spl; 89 compatible = "jedec,spi-nor"; 90 label = "sfc_nor"; 91 reg = <0>; 92 spi-tx-bus-width = <1>; 93 spi-rx-bus-width = <4>; 94 spi-max-frequency = <100000000>; 95 }; 96}; 97 98&sdhci { 99 bus-width = <8>; 100 u-boot,dm-spl; 101 /delete-property/ assigned-clocks; 102 /delete-property/ assigned-clock-rates; 103 /delete-property/ pinctrl-names; 104 /delete-property/ pinctrl-0; 105 mmc-hs400-1_8v; 106 mmc-hs400-enhanced-strobe; 107 fixed-emmc-driver-type = <1>; 108 status = "okay"; 109}; 110 111&sdmmc { 112 u-boot,dm-spl; 113 status = "okay"; 114}; 115 116&saradc { 117 u-boot,dm-pre-reloc; 118 status = "okay"; 119}; 120 121&u2phy_otg { 122 u-boot,dm-pre-reloc; 123 status = "okay"; 124}; 125 126&usb2phy { 127 u-boot,dm-pre-reloc; 128 status = "okay"; 129}; 130 131&firmware { 132 u-boot,dm-spl; 133}; 134 135&scmi { 136 u-boot,dm-spl; 137}; 138 139&scmi_clk { 140 u-boot,dm-spl; 141}; 142 143&scmi_shmem { 144 u-boot,dm-spl; 145}; 146 147&pinctrl { 148 u-boot,dm-spl; 149 status = "okay"; 150}; 151 152&gpio0 { 153 u-boot,dm-spl; 154}; 155 156&gpio1 { 157 u-boot,dm-spl; 158}; 159 160&gpio2 { 161 u-boot,dm-spl; 162}; 163 164&pcfg_pull_none_drv_level_1 { 165 u-boot,dm-spl; 166}; 167 168&pcfg_pull_none_drv_level_2 { 169 u-boot,dm-spl; 170}; 171 172&pcfg_pull_up_drv_level_1 { 173 u-boot,dm-spl; 174}; 175 176&pcfg_pull_up_drv_level_2 { 177 u-boot,dm-spl; 178}; 179 180&pcfg_pull_up { 181 u-boot,dm-spl; 182}; 183 184&pcfg_pull_none { 185 u-boot,dm-spl; 186}; 187 188&sdmmc_pins { 189 u-boot,dm-spl; 190}; 191 192&sdmmc_bus4 { 193 u-boot,dm-spl; 194}; 195 196&sdmmc_clk { 197 u-boot,dm-spl; 198}; 199 200&sdmmc_cmd { 201 u-boot,dm-spl; 202}; 203 204&sdmmc_det { 205 u-boot,dm-spl; 206}; 207