xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rv1106-u-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	aliases {
9*4882a593Smuzhiyun		mmc1 = &sdmmc;
10*4882a593Smuzhiyun		mmc0 = &emmc;
11*4882a593Smuzhiyun	};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	chosen {
14*4882a593Smuzhiyun		stdout-path = &uart2;
15*4882a593Smuzhiyun		u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	secure-otp@ff3fd8000 {
19*4882a593Smuzhiyun		compatible = "rockchip,rv1106-secure-otp";
20*4882a593Smuzhiyun		reg = <0xff3d8000 0x4000>;
21*4882a593Smuzhiyun		secure_conf = <0xff07a018>;
22*4882a593Smuzhiyun		cru_rst_addr = <0xff3bca08>;
23*4882a593Smuzhiyun		mask_addr = <0xff3dc000>;
24*4882a593Smuzhiyun		u-boot,dm-spl;
25*4882a593Smuzhiyun		status = "okay";
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun&emmc {
30*4882a593Smuzhiyun	mmc-ecsd = <0x3F000>;
31*4882a593Smuzhiyun	bus-width = <8>;
32*4882a593Smuzhiyun	mmc-hs200-1_8v;
33*4882a593Smuzhiyun	u-boot,dm-spl;
34*4882a593Smuzhiyun	status = "okay";
35*4882a593Smuzhiyun};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun&cru {
38*4882a593Smuzhiyun	u-boot,dm-spl;
39*4882a593Smuzhiyun	status = "okay";
40*4882a593Smuzhiyun};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun&gmac {
43*4882a593Smuzhiyun	u-boot,dm-spl;
44*4882a593Smuzhiyun	status = "okay";
45*4882a593Smuzhiyun};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun&grf {
48*4882a593Smuzhiyun	u-boot,dm-spl;
49*4882a593Smuzhiyun	status = "okay";
50*4882a593Smuzhiyun};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun&grf_cru {
53*4882a593Smuzhiyun	u-boot,dm-spl;
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun&mdio {
58*4882a593Smuzhiyun	u-boot,dm-spl;
59*4882a593Smuzhiyun	status = "okay";
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&rmii_phy {
63*4882a593Smuzhiyun	u-boot,dm-spl;
64*4882a593Smuzhiyun	status = "okay";
65*4882a593Smuzhiyun};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun&sdmmc {
68*4882a593Smuzhiyun	u-boot,dm-spl;
69*4882a593Smuzhiyun	status = "okay";
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&sdmmc0 {
73*4882a593Smuzhiyun	u-boot,dm-spl;
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&sdmmc0_bus4 {
77*4882a593Smuzhiyun	u-boot,dm-spl;
78*4882a593Smuzhiyun};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun&sdmmc0_clk {
81*4882a593Smuzhiyun	u-boot,dm-spl;
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&sdmmc0_cmd {
85*4882a593Smuzhiyun	u-boot,dm-spl;
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&sdmmc0_det {
89*4882a593Smuzhiyun	u-boot,dm-spl;
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&pinctrl {
93*4882a593Smuzhiyun	u-boot,dm-spl;
94*4882a593Smuzhiyun	status = "okay";
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&ioc {
98*4882a593Smuzhiyun	u-boot,dm-spl;
99*4882a593Smuzhiyun	status = "okay";
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&pmuioc {
103*4882a593Smuzhiyun	u-boot,dm-spl;
104*4882a593Smuzhiyun	status = "okay";
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&pcfg_pull_up_drv_level_2 {
108*4882a593Smuzhiyun	u-boot,dm-spl;
109*4882a593Smuzhiyun};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&pcfg_pull_up {
112*4882a593Smuzhiyun	u-boot,dm-spl;
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&gpio0 {
116*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
117*4882a593Smuzhiyun	status = "okay";
118*4882a593Smuzhiyun};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun&gpio1 {
121*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun&gpio2 {
126*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
127*4882a593Smuzhiyun	status = "okay";
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&gpio3 {
131*4882a593Smuzhiyun	u-boot,dm-spl;
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&gpio4 {
136*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
137*4882a593Smuzhiyun	status = "okay";
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&crypto {
141*4882a593Smuzhiyun	u-boot,dm-spl;
142*4882a593Smuzhiyun	clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
143*4882a593Smuzhiyun	clock-frequency = <300000000>, <300000000>;
144*4882a593Smuzhiyun	status = "okay";
145*4882a593Smuzhiyun};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun&rng {
148*4882a593Smuzhiyun	u-boot,dm-spl;
149*4882a593Smuzhiyun	status = "okay";
150*4882a593Smuzhiyun};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun&saradc {
153*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&sfc {
158*4882a593Smuzhiyun	u-boot,dm-spl;
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	#address-cells = <1>;
162*4882a593Smuzhiyun	#size-cells = <0>;
163*4882a593Smuzhiyun	spi_nand: flash@0 {
164*4882a593Smuzhiyun		u-boot,dm-spl;
165*4882a593Smuzhiyun		compatible = "spi-nand";
166*4882a593Smuzhiyun		reg = <0>;
167*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
168*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
169*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	spi_nor: flash@1 {
173*4882a593Smuzhiyun		u-boot,dm-spl;
174*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
175*4882a593Smuzhiyun		label = "sfc_nor";
176*4882a593Smuzhiyun		reg = <0>;
177*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
178*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
179*4882a593Smuzhiyun		spi-max-frequency = <100000000>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun&u2phy {
184*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&u2phy_otg {
189*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
190*4882a593Smuzhiyun	status = "okay";
191*4882a593Smuzhiyun};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun&usbdrd {
194*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
195*4882a593Smuzhiyun	status = "okay";
196*4882a593Smuzhiyun};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun&usbdrd_dwc3 {
199*4882a593Smuzhiyun	u-boot,dm-pre-reloc;
200*4882a593Smuzhiyun	status = "okay";
201*4882a593Smuzhiyun};
202