1*4882a593Smuzhiyun* NXP SPI Flash Interface (SPIFI) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunNXP SPIFI is a specialized SPI interface for serial Flash devices. 4*4882a593SmuzhiyunIt supports one Flash device with 1-, 2- and 4-bits width in SPI 5*4882a593Smuzhiyunmode 0 or 3. The controller operates in either command or memory 6*4882a593Smuzhiyunmode. In memory mode the Flash is accessible from the CPU as 7*4882a593Smuzhiyunnormal memory. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun - compatible : Should be "nxp,lpc1773-spifi" 11*4882a593Smuzhiyun - reg : the first contains the register location and length, 12*4882a593Smuzhiyun the second contains the memory mapping address and length 13*4882a593Smuzhiyun - reg-names: Should contain the reg names "spifi" and "flash" 14*4882a593Smuzhiyun - interrupts : Should contain the interrupt for the device 15*4882a593Smuzhiyun - clocks : The clocks needed by the SPIFI controller 16*4882a593Smuzhiyun - clock-names : Should contain the clock names "spifi" and "reg" 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun - resets : phandle + reset specifier 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe SPI Flash must be a child of the SPIFI node and must have a 22*4882a593Smuzhiyuncompatible property as specified in bindings/mtd/jedec,spi-nor.txt 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptionally it can also contain the following properties. 25*4882a593Smuzhiyun - spi-cpol : Controller only supports mode 0 and 3 so either 26*4882a593Smuzhiyun both spi-cpol and spi-cpha should be present or 27*4882a593Smuzhiyun none of them 28*4882a593Smuzhiyun - spi-cpha : See above 29*4882a593Smuzhiyun - spi-rx-bus-width : Used to select how many pins that are used 30*4882a593Smuzhiyun for input on the controller 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunSee bindings/spi/spi-bus.txt for more information. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyunspifi: spifi@40003000 { 36*4882a593Smuzhiyun compatible = "nxp,lpc1773-spifi"; 37*4882a593Smuzhiyun reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; 38*4882a593Smuzhiyun reg-names = "spifi", "flash"; 39*4882a593Smuzhiyun interrupts = <30>; 40*4882a593Smuzhiyun clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; 41*4882a593Smuzhiyun clock-names = "spifi", "reg"; 42*4882a593Smuzhiyun resets = <&rgu 53>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun flash@0 { 45*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 46*4882a593Smuzhiyun spi-cpol; 47*4882a593Smuzhiyun spi-cpha; 48*4882a593Smuzhiyun spi-rx-bus-width = <4>; 49*4882a593Smuzhiyun #address-cells = <1>; 50*4882a593Smuzhiyun #size-cells = <1>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun partition@0 { 53*4882a593Smuzhiyun label = "data"; 54*4882a593Smuzhiyun reg = <0 0x200000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59