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Searched refs:TOP_CKG_HVD_IDB_432MHZ (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h474 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c3911 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3968 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h475 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c4067 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4110 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h491 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c4041 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4084 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h475 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c3952 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4009 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h476 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c4002 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4059 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h474 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) macro
H A DhalHVD_EX.c3906 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h491 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c4062 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4105 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h475 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this macro
H A DhalHVD_EX.c4089 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4132 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h611 #define TOP_CKG_HVD_IDB_432MHZ BITS(2:0, 0) // default use this macro
H A DhalHVD_EX.c4249 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4265 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h507 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 4) macro
H A DhalHVD_EX.c4005 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4062 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h730 #define TOP_CKG_HVD_IDB_432MHZ BITS(2:0, 0) // default use this macro
H A DhalHVD_EX.c4950 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4962 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h730 #define TOP_CKG_HVD_IDB_432MHZ BITS(2:0, 0) // default use this macro
H A DhalHVD_EX.c4935 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4947 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()