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Searched refs:TOP_CKG_HVD_AEC_288MHZ (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c3907 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3915 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3923 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3931 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3939 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3964 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h512 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c3963 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3968 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3973 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3978 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3998 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
H A DregHVD_EX.h529 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c3912 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3920 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3928 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3936 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3969 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h512 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c4006 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4014 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4022 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4030 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4063 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h543 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 2) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c3953 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3961 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3969 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3977 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4010 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h513 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c4003 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4011 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4019 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4027 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4060 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h514 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c4011 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4016 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4021 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4026 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4046 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
H A DregHVD_EX.h513 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c3984 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3989 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3994 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3999 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4019 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
H A DregHVD_EX.h529 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c3989 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3994 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
3999 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4004 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4024 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
H A DregHVD_EX.h513 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h620 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
H A DhalHVD_EX.c4250 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4266 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h739 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
H A DhalHVD_EX.c4897 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4907 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h739 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this macro
H A DhalHVD_EX.c4882 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()
4892 … _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK); in HAL_AEC_PowerCtrl()