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Searched refs:REG_TOP_VP8 (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c3900 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
3906 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3911 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3916 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3926 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3931 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3936 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3941 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3948 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
[all …]
H A DregHVD_EX.h514 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c3876 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3883 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3899 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3908 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3916 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3924 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3940 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3948 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3956 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h497 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c3881 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3888 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3904 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3913 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3929 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3945 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3953 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3961 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h497 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c3975 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3982 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3998 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4007 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4015 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4023 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4031 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4039 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4047 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4055 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h526 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c3922 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3929 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3945 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3970 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3978 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3986 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
3994 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4002 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h498 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c3972 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3979 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
3995 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4004 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4012 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4020 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4028 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4036 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4044 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4052 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h499 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c3948 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3959 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3964 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3969 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3974 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3979 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3984 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3989 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3996 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
[all …]
H A DregHVD_EX.h498 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c3921 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
3927 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3947 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3952 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3957 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3969 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
[all …]
H A DregHVD_EX.h514 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c3926 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3947 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3952 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3957 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3967 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
3974 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
[all …]
H A DregHVD_EX.h498 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c4222 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
4228 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_HVD_EX_PowerCtrl()
4242 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4251 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4259 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
4267 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
H A DregHVD_EX.h625 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DhalHVD_EX.c4844 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
4850 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4855 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4860 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4867 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h744 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DhalHVD_EX.c4859 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
4865 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4870 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4875 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK); in HAL_VP8_PowerCtrl()
4882 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS); in HAL_VP8_PowerCtrl()
H A DregHVD_EX.h744 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DregHVD_EX.h748 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) macro

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