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Searched refs:reg_write (Results 1 – 25 of 34) sorted by relevance

12

/rk3399_rockchip-uboot/board/micronas/vct/
H A Debi_smc911x.c17 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); in ebi_init_smc911x()
18 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in ebi_init_smc911x()
20 reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); in ebi_init_smc911x()
21 reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); in ebi_init_smc911x()
23 reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); in ebi_init_smc911x()
24 reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); in ebi_init_smc911x()
26 reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); in ebi_init_smc911x()
27 reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); in ebi_init_smc911x()
41 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in smc911x_reg_read()
43 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); in smc911x_reg_read()
[all …]
H A Debi_onenand.c17 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); in ebi_nand_read_word()
26 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); in ebi_nand_write_word()
27 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_nand_write_word()
37 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_onenand()
39 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
40 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_onenand()
42 reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand()
43 reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ in ebi_init_onenand()
45 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); in ebi_init_onenand()
46 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); in ebi_init_onenand()
[all …]
H A Debi_nor_flash.c15 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); in ebi_read()
29 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); in ebi_write_u16()
30 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_write_u16()
65 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash()
67 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); in ebi_init_nor_flash()
68 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_nor_flash()
70 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); in ebi_init_nor_flash()
71 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); in ebi_init_nor_flash()
72 reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); in ebi_init_nor_flash()
73 reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); in ebi_init_nor_flash()
[all …]
H A Dtop.c73 reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); in top_write_pin()
76 reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); in top_write_pin()
79 reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); in top_write_pin()
82 reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); in top_write_pin()
91 reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_write_pin()
95 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_write_pin()
133 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_set_pin()
H A Dehci.c78 reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); in vct_ehci_hcd_init()
81 reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003); in vct_ehci_hcd_init()
83 reg_write(USBH_USBMODE(USBH_BASE), 0x00000007); in vct_ehci_hcd_init()
90 reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); in vct_ehci_hcd_init()
H A Dvct.c50 reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT); in _machine_restart()
51 reg_write(WDT_TORR(WDT_BASE), 0x00); in _machine_restart()
52 reg_write(WDT_CR(WDT_BASE), 0x1D); in _machine_restart()
H A Debi.c30 reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); in ebi_initialize()
H A Ddcgu.c120 reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg); in dcgu_set_clk_switch()
123 reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); in dcgu_set_clk_switch()
242 reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg); in dcgu_set_reset_switch()
/rk3399_rockchip-uboot/board/Synology/ds414/
H A Dds414.c134 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f()
135 reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); in board_early_init_f()
136 reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); in board_early_init_f()
139 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f()
140 reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); in board_early_init_f()
141 reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); in board_early_init_f()
144 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f()
145 reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); in board_early_init_f()
146 reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); in board_early_init_f()
149 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); in board_early_init_f()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_lib.c316 reg_write(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
334 reg_write(CORE_AVS_CONTROL_0REG, core_avs); in serdes_phy_config()
340 reg_write(CORE_AVS_CONTROL_2REG, core_avs); in serdes_phy_config()
347 reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2); in serdes_phy_config()
352 reg_write(CPU_AVS_CONTROL2_REG, cpu_avs); in serdes_phy_config()
370 reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111); in serdes_phy_config()
374 reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */ in serdes_phy_config()
376 reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */ in serdes_phy_config()
378 reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
380 reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */ in serdes_phy_config()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c79 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw()
88 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
92 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
165 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_write_leveling_hw()
224 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
227 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_wl_supplement()
259 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
404 reg_write(REG_DRAM_TRAINING_2_ADDR, in ddr3_wl_supplement()
454 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_wl_supplement()
458 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_wl_supplement()
[all …]
H A Dxor.c42 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
46 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
48 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
72 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
75 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init()
89 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish()
91 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish()
93 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish()
95 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
150 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
[all …]
H A Dddr3_init.c160 reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]); in ddr3_restore_and_set_final_windows()
166 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows()
176 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
180 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg); in ddr3_restore_and_set_final_windows()
193 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); in ddr3_restore_and_set_final_windows()
206 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows()
223 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
251 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
254 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
258 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
[all …]
H A Dddr3_spd.c777 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
784 reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg);
850 reg_write(REG_SDRAM_TIMING_LOW_ADDR, reg);
864 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);
933 reg_write(REG_SDRAM_ADDRESS_CTRL_ADDR, reg);
941 reg_write(REG_SDRAM_OPERATION_ADDR, reg);
945 reg_write(REG_SDRAM_EXT_MODE_ADDR, reg);
953 reg_write(REG_DDR_CONT_HIGH_ADDR, reg);
960 reg_write(0x142C, reg);
965 reg_write(REG_MBUS_CPU_BLOCK_ADDR, 0x0000E907);
[all …]
H A Dddr3_hw_training.c110 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
542 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params()
563 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
565 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
584 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
586 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_write_pup_reg()
604 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
607 reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */ in ddr3_read_pup_reg()
630 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns()
633 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_load_patterns()
[all …]
H A Dddr3_read_leveling.c77 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
81 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_read_leveling_hw()
194 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
199 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
212 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
225 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
240 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
302 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
312 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_read_leveling_sw()
315 reg_write(REG_DRAM_TRAINING_ADDR, 0); /* 0x15B0 - Training Register */ in ddr3_read_leveling_sw()
[all …]
H A Dddr3_pbs.c113 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
117 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
164 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
288 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
385 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_tx()
389 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_pbs_tx()
556 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
560 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_rx()
606 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_pbs_rx()
678 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_pbs_rx()
[all …]
H A Dddr3_dqs.c144 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
148 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_rx()
163 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
190 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
197 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_rx()
201 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_dqs_centralization_rx()
226 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
230 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_dqs_centralization_tx()
243 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
270 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_dqs_centralization_tx()
[all …]
H A Dddr3_sdram.c71 reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)), in xor_waiton_eng()
512 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
519 reg_write(XOR_ADDR_OVRD_REG(0, 0), in ddr3_dram_sram_burst()
647 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
655 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_reset_phy_read_fifo()
668 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_reset_phy_read_fifo()
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dxor.c48 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init()
73 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init()
76 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x7fff0000); in mv_sys_xor_init()
90 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish()
92 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish()
95 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish()
98 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish()
152 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
177 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
183 reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); in mv_xor_mem_init()
[all …]
H A Dddr3_init.c189 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]); in ddr3_restore_and_set_final_windows()
207 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg); in ddr3_restore_and_set_final_windows()
229 reg_write(ADDRESS_FILTERING_END_REGISTER, 0); in ddr3_save_and_set_training_windows()
236 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows()
264 reg_write(win_ctrl_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
268 reg_write(win_base_reg + win_jump_index * tmp_count, in ddr3_save_and_set_training_windows()
272 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows()
354 reg_write(REG_TRAINING_DEBUG_3_ADDR, reg); in ddr3_init()
362 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); in ddr3_init()
406 reg_write(REG_BOOTROM_ROUTINE_ADDR, in ddr3_init()
[all …]
/rk3399_rockchip-uboot/drivers/spi/
H A Dmxc_spi.c36 #define reg_write(a, v) writel(v, a) macro
147 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
149 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
203 reg_write(&regs->ctrl, reg_ctrl); in spi_cfg_mxc()
205 reg_write(&regs->cfg, reg_config); in spi_cfg_mxc()
212 reg_write(&regs->intr, 0); in spi_cfg_mxc()
213 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
235 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); in spi_xchg_single()
237 reg_write(&regs->cfg, mxcs->cfg_reg); in spi_xchg_single()
241 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A Ddram.c132 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg); in mv_xor_init2()
139 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_init2()
145 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size); in mv_xor_init2()
155 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), in mv_xor_finish2()
157 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
159 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), in mv_xor_finish2()
179 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
209 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.c48 reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp); in hws_pex_config()
81 reg_write(SOC_CTRL_REG, tmp); in hws_pex_config()
177 reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); in hws_pex_config()
183 reg_write(PEX_CTRL_REG(pex_idx), tmp); in hws_pex_config()
220 reg_write(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
244 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_bus_num_set()
259 reg_write(PEX_STATUS_REG(pex_if), pex_status); in pex_local_dev_num_set()
335 reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data); in pex_config_read()
H A Dsys_env_lib.c127 reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()
132 reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg); in sys_env_suspend_wakeup_check()

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