110 		reg_write(REG_SDRAM_CONFIG_ADDR, reg);  in ddr3_hw_training()
542 	reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg);  in ddr3_set_performance_params()
563 	reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg);	/* 0x16A0 */  in ddr3_write_pup_reg()
565 	reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg);	/* 0x16A0 */  in ddr3_write_pup_reg()
584 		reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */  in ddr3_write_pup_reg()
586 		reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg); /* 0x16A0 */  in ddr3_write_pup_reg()
604 	reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg);	/* 0x16A0 */  in ddr3_read_pup_reg()
607 	reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, reg);	/* 0x16A0 */  in ddr3_read_pup_reg()
630 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_load_patterns()
633 	reg_write(REG_DRAM_TRAINING_ADDR, reg);	/* 0x15B0 - Training Register */  in ddr3_load_patterns()
647 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_load_patterns()
651 	reg_write(REG_DRAM_TRAINING_1_ADDR, reg);  in ddr3_load_patterns()
655 	reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0);  in ddr3_load_patterns()
658 		reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0);  in ddr3_load_patterns()
660 		reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR,  in ddr3_load_patterns()
675 	reg_write(REG_DRAM_TRAINING_ADDR, reg);  in ddr3_load_patterns()
847 		reg_write(REG_PHY_REGISTRY_FILE_ACCESS_ADDR, val);  in ddr3_read_training_results()
856 	reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, val);	/* reg 0x1538 */  in ddr3_read_training_results()
858 	reg_write(REG_READ_DATA_READY_DELAYS_ADDR, val);	/* reg 0x153c */  in ddr3_read_training_results()
928 	reg_write(REG_DRAM_TRAINING_ADDR, reg);	/* 0x15B0 - Training Register */  in ddr3_training_suspend_resume()
936 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_training_suspend_resume()
943 	reg_write(REG_DRAM_TRAINING_ADDR, reg);	/* 0x15B0 - Training Register */  in ddr3_training_suspend_resume()
1081 	reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg);  in ddr3_odt_activate()
1112 	reg_write(REG_ODT_TIME_LOW_ADDR, reg);  in ddr3_odt_read_dynamic_config()