1ae691e57SStefan Roese /*
2ae691e57SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
3ae691e57SStefan Roese *
4ae691e57SStefan Roese * Original Author Guenter Gebhardt
5ae691e57SStefan Roese * Copyright (C) 2006 Micronas GmbH
6ae691e57SStefan Roese *
7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
8ae691e57SStefan Roese */
9ae691e57SStefan Roese
10ae691e57SStefan Roese #include <common.h>
11ae691e57SStefan Roese
12ae691e57SStefan Roese #include "vct.h"
13ae691e57SStefan Roese
vct_ehci_hcd_init(u32 * hccr,u32 * hcor)14ae691e57SStefan Roese int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
15ae691e57SStefan Roese {
16ae691e57SStefan Roese int retval;
17ae691e57SStefan Roese u32 val;
18ae691e57SStefan Roese u32 addr;
19ae691e57SStefan Roese
20ae691e57SStefan Roese dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
21ae691e57SStefan Roese dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
22ae691e57SStefan Roese dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
23ae691e57SStefan Roese dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
24ae691e57SStefan Roese dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
25ae691e57SStefan Roese
26ae691e57SStefan Roese /* Wait until (DCGU_USBPHY_STAT == 7) */
27ae691e57SStefan Roese addr = DCGU_USBPHY_STAT(DCGU_BASE);
28ae691e57SStefan Roese val = reg_read(addr);
29ae691e57SStefan Roese while (val != 7)
30ae691e57SStefan Roese val = reg_read(addr);
31ae691e57SStefan Roese
32ae691e57SStefan Roese dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
33ae691e57SStefan Roese dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
34ae691e57SStefan Roese
35ae691e57SStefan Roese retval = scc_reset(SCC_USB_RW, 0);
36ae691e57SStefan Roese if (retval) {
37ae691e57SStefan Roese printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
38ae691e57SStefan Roese return retval;
39ae691e57SStefan Roese } else {
40ae691e57SStefan Roese retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
41ae691e57SStefan Roese if (retval) {
42ae691e57SStefan Roese printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
43ae691e57SStefan Roese retval);
44ae691e57SStefan Roese return retval;
45ae691e57SStefan Roese }
46ae691e57SStefan Roese }
47ae691e57SStefan Roese
48ae691e57SStefan Roese if (!retval) {
49ae691e57SStefan Roese /*
50ae691e57SStefan Roese * For the AGU bypass, where the SCC client provides full
51ae691e57SStefan Roese * physical address
52ae691e57SStefan Roese */
53ae691e57SStefan Roese scc_set_usb_address_generation_mode(1);
54ae691e57SStefan Roese scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
55ae691e57SStefan Roese USE_NO_FH, DMA_READ, 0);
56ae691e57SStefan Roese scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
57ae691e57SStefan Roese USE_NO_FH, DMA_WRITE, 0);
58ae691e57SStefan Roese scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
59ae691e57SStefan Roese USE_NO_FH, DMA_WRITE, 0);
60ae691e57SStefan Roese scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
61ae691e57SStefan Roese USE_NO_FH, DMA_READ, 0);
62ae691e57SStefan Roese
63ae691e57SStefan Roese /* Enable memory interface */
64ae691e57SStefan Roese scc_enable(SCC_USB_RW, 1);
65ae691e57SStefan Roese
66ae691e57SStefan Roese /* Start (start_cmd=0) DMAs */
67ae691e57SStefan Roese scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
68ae691e57SStefan Roese scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
69ae691e57SStefan Roese } else {
70ae691e57SStefan Roese printf("Cannot configure USB memory channel.\n");
71ae691e57SStefan Roese printf("USB can not access RAM. SCC configuration failed.\n");
72ae691e57SStefan Roese return retval;
73ae691e57SStefan Roese }
74ae691e57SStefan Roese
75ae691e57SStefan Roese /* Wait a short while */
76ae691e57SStefan Roese udelay(300000);
77ae691e57SStefan Roese
78ae691e57SStefan Roese reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
79ae691e57SStefan Roese
80ae691e57SStefan Roese /* Set EHCI structures and DATA in RAM */
81ae691e57SStefan Roese reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
82ae691e57SStefan Roese /* Set USBMODE to bigendian and set host mode */
83ae691e57SStefan Roese reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
84ae691e57SStefan Roese
85ae691e57SStefan Roese /*
86ae691e57SStefan Roese * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
87ae691e57SStefan Roese * 512 byte USB transfers on the bulk pipe to work properly.
88ae691e57SStefan Roese * Set USBH_BURSTSIZE to 0x00001c1c
89ae691e57SStefan Roese */
90ae691e57SStefan Roese reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
91ae691e57SStefan Roese
92ae691e57SStefan Roese /* Insert access register addresses */
93ae691e57SStefan Roese *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
94ae691e57SStefan Roese *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
95ae691e57SStefan Roese
96ae691e57SStefan Roese return 0;
97ae691e57SStefan Roese }
98