160 		reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);  in ddr3_restore_and_set_final_windows()
166 	reg_write(0x8c04, 0x40000000);  in ddr3_restore_and_set_final_windows()
176 			reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);  in ddr3_restore_and_set_final_windows()
180 			reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);  in ddr3_restore_and_set_final_windows()
193 	reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);  in ddr3_restore_and_set_final_windows()
206 	reg_write(0x8c04, 0);  in ddr3_save_and_set_training_windows()
223 	reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);  in ddr3_save_and_set_training_windows()
251 			reg_write(win_ctrl_reg + win_jump_index * tmp_count,  in ddr3_save_and_set_training_windows()
254 			reg_write(win_base_reg + win_jump_index * tmp_count,  in ddr3_save_and_set_training_windows()
258 				reg_write(win_remap_reg +  in ddr3_save_and_set_training_windows()
396 	reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);  in ddr3_init_main()
476 		reg_write(REG_SDRAM_CONFIG_ADDR, reg);  in ddr3_init_main()
524 	reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);  in ddr3_init_main()
533 	reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);  in ddr3_init_main()
536 	reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);  in ddr3_init_main()
537 	reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);  in ddr3_init_main()
542 		reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);  in ddr3_init_main()
543 		reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);  in ddr3_init_main()
552 	reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);  in ddr3_init_main()
557 		reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);  in ddr3_init_main()
560 	reg_write(DLB_AGING_REGISTER, 0x0f7f007f);  in ddr3_init_main()
561 	reg_write(DLB_EVICTION_CONTROL_REG, 0x0);  in ddr3_init_main()
562 	reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);  in ddr3_init_main()
564 	reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);  in ddr3_init_main()
565 	reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);  in ddr3_init_main()
566 	reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);  in ddr3_init_main()
567 	reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);  in ddr3_init_main()
574 		reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);  in ddr3_init_main()
591 	reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);  in ddr3_init_main()
621 	reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);  in ddr3_init_main()
646 	reg_write(REG_SDRAM_CONFIG_ADDR, reg);  in ddr3_init_main()
656 	reg_write(REG_BOOTROM_ROUTINE_ADDR,  in ddr3_init_main()
664 			reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));  in ddr3_init_main()
668 	reg_write(DLB_EVICTION_CONTROL_REG, 0x9);  in ddr3_init_main()
673 	reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);  in ddr3_init_main()
792 		reg_write(ddr_mode->vals[j].reg_addr,  in ddr3_static_training_init()
890 		reg_write(ddr_mode->regs[j].reg_addr,  in ddr3_static_mc_init()