77 	reg_write(REG_DRAM_TRAINING_ADDR, reg);	/* 0x15B0 - Training Register */  in ddr3_read_leveling_hw()
81 	reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg);  in ddr3_read_leveling_hw()
194 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_sw()
199 	reg_write(REG_DRAM_TRAINING_ADDR, reg);	/* 0x15B0 - Training Register */  in ddr3_read_leveling_sw()
212 			reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_sw()
225 			reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg);  in ddr3_read_leveling_sw()
240 			reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);  in ddr3_read_leveling_sw()
302 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_sw()
312 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_sw()
315 	reg_write(REG_DRAM_TRAINING_ADDR, 0);	/* 0x15B0 - Training Register */  in ddr3_read_leveling_sw()
325 	reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_sw()
449 		reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_single_cs_rl_mode()
624 					reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR,  in ddr3_read_leveling_single_cs_rl_mode()
672 				reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);  in ddr3_read_leveling_single_cs_rl_mode()
727 	reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);  in ddr3_read_leveling_single_cs_rl_mode()
803 		reg_write(REG_DRAM_TRAINING_2_ADDR, reg);  in ddr3_read_leveling_single_cs_window_mode()
1029 					reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR,  in ddr3_read_leveling_single_cs_window_mode()
1074 				reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);  in ddr3_read_leveling_single_cs_window_mode()
1202 	reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);  in ddr3_read_leveling_single_cs_window_mode()