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Searched refs:reg (Results 1 – 25 of 1574) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c71 u32 reg; in wait_refresh_op_complete() local
75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
135 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
144 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
146 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_write_leveling.c67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
76 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
77 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
80 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
84 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
86 reg |= (COUNT_HW_WL << REG_DRAM_TRAINING_RETEST_OFFS); in ddr3_write_leveling_hw()
87 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
88 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
90 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_write_leveling_hw()
92 reg_write(REG_DRAM_TRAINING_SHADOW_ADDR, reg); in ddr3_write_leveling_hw()
[all …]
H A Dddr3_hw_training.c84 u32 freq, reg; in ddr3_hw_training() local
106 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
107 if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) { in ddr3_hw_training()
109 reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS); in ddr3_hw_training()
110 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
115 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
116 if (reg & (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS)) in ddr3_hw_training()
124 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
125 dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) & in ddr3_hw_training()
130 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Danalogix_dp_reg.c37 static void analogix_dp_write(struct analogix_dp_device *dp, u32 reg, u32 val) in analogix_dp_write() argument
40 writel(val, dp->reg_base + reg); in analogix_dp_write()
41 writel(val, dp->reg_base + reg); in analogix_dp_write()
44 static u32 analogix_dp_read(struct analogix_dp_device *dp, u32 reg) in analogix_dp_read() argument
46 readl(dp->reg_base + reg); in analogix_dp_read()
48 return readl(dp->reg_base + reg); in analogix_dp_read()
53 u32 reg; in analogix_dp_enable_video_mute() local
56 reg = analogix_dp_read(dp, ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
57 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
58 analogix_dp_write(dp, ANALOGIX_DP_VIDEO_CTL_1, reg); in analogix_dp_enable_video_mute()
[all …]
/rk3399_rockchip-uboot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c25 unsigned int reg; in exynos_dp_enable_video_input() local
27 reg = readl(&dp_regs->video_ctl1); in exynos_dp_enable_video_input()
28 reg &= ~VIDEO_EN_MASK; in exynos_dp_enable_video_input()
32 reg |= VIDEO_EN_MASK; in exynos_dp_enable_video_input()
34 writel(reg, &dp_regs->video_ctl1); in exynos_dp_enable_video_input()
42 unsigned int reg; in exynos_dp_enable_video_bist() local
44 reg = readl(&dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
45 reg &= ~VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
49 reg |= VIDEO_BIST_MASK; in exynos_dp_enable_video_bist()
51 writel(reg, &dp_regs->video_ctl4); in exynos_dp_enable_video_bist()
[all …]
H A Dexynos_mipi_dsi_lowlevel.c21 unsigned int reg; in exynos_mipi_dsi_func_reset() local
26 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
28 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
30 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
35 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
40 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
43 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
45 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
52 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Darm32_macros.S8 .macro read_midr reg argument
9 mrc p15, 0, \reg, c0, c0, 0
12 .macro read_ctr reg argument
13 mrc p15, 0, \reg, c0, c0, 1
16 .macro read_mpidr reg argument
17 mrc p15, 0, \reg, c0, c0, 5
20 .macro read_sctlr reg argument
21 mrc p15, 0, \reg, c1, c0, 0
24 .macro write_sctlr reg argument
25 mcr p15, 0, \reg, c1, c0, 0
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c35 u32 reg; in wb_start() local
43 : "=r"(reg) /* output */ in wb_start()
47 if (reg != NV_WB_RUN_ADDRESS) in wb_start()
56 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
57 reg |= SWR_CSITE_RST; in wb_start()
58 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]); in wb_start()
69 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START; in wb_start()
70 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
76 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
77 reg |= CPU_CLMP; in wb_start()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-38x-controlcenterdc.dts60 reg = <0x00000000 0x10000000>; /* 256 MB */
80 reg = <0>;
97 reg = <0>; /* Chip select 0 */
104 reg = <1>; /* Chip select 1 */
116 reg = <0x21>;
123 reg = <0x22>;
129 reg = <0x23>;
135 reg = <0x24>;
141 reg = <0x25>;
147 reg = <0x26>;
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c151 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
181 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
182 reg &= 0xFF9FFFFF; in setup_serdes_volt()
183 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
191 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
192 reg &= 0xFF9FFFFF; in setup_serdes_volt()
193 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
201 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
202 reg &= 0xFFFFFFBF; in setup_serdes_volt()
203 reg |= 0x10000000; in setup_serdes_volt()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c30 u32 reg; in enable_ocotp_clk() local
32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
34 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
36 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; in enable_ocotp_clk()
37 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
84 u32 reg; in enable_usboh3_clk() local
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
88 reg |= MXC_CCM_CCGR6_USBOH3_MASK; in enable_usboh3_clk()
90 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK); in enable_usboh3_clk()
91 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
[all …]
/rk3399_rockchip-uboot/drivers/watchdog/
H A Dorion_wdt.c25 void __iomem *reg; member
47 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_reset()
55 u32 reg; in orion_wdt_start() local
60 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
61 reg |= WDT_AXP_FIXED_ENABLE_BIT; in orion_wdt_start()
62 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
65 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_start()
68 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
69 reg &= ~WDT_A370_EXPIRED; in orion_wdt_start()
70 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
[all …]
/rk3399_rockchip-uboot/board/micronas/vct/
H A Dtop.c14 u32 reg; member
29 TOP_PINMUX_t reg; in top_read_pin() local
36 reg.reg = 0xdeadbeef; in top_read_pin()
39 reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); in top_read_pin()
42 reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); in top_read_pin()
45 reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); in top_read_pin()
48 reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); in top_read_pin()
57 reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_read_pin()
61 reg.reg = reg_read(TOP_BASE + (pin * 4)); in top_read_pin()
65 return reg; in top_read_pin()
[all …]
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h45 void msg_port_setup(int op, int port, int reg);
55 u32 msg_port_read(u8 port, u32 reg);
64 void msg_port_write(u8 port, u32 reg, u32 value);
74 u32 msg_port_alt_read(u8 port, u32 reg);
83 void msg_port_alt_write(u8 port, u32 reg, u32 value);
93 u32 msg_port_io_read(u8 port, u32 reg);
102 void msg_port_io_write(u8 port, u32 reg, u32 value);
109 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
110 msg_port_##type##_write(port, reg, \
111 (msg_port_##type##_read(port, reg) \
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/rk3399_rockchip-uboot/drivers/spi/
H A Dcadence_qspi_apb.c188 unsigned int reg; in cadence_qspi_apb_controller_enable() local
189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
190 reg |= CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_enable()
191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
196 unsigned int reg; in cadence_qspi_apb_controller_disable() local
197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
198 reg &= ~CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_disable()
199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
232 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
235 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
[all …]
/rk3399_rockchip-uboot/drivers/power/power_delivery/
H A Dtcpci.c20 #define tcpc_presenting_cc1_rd(reg) \ argument
21 (!(TCPC_ROLE_CTRL_DRP & (reg)) && \
22 (((reg) & (TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT)) == \
24 #define tcpc_presenting_cc2_rd(reg) \ argument
25 (!(TCPC_ROLE_CTRL_DRP & (reg)) && \
26 (((reg) & (TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT)) == \
53 static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val) in tcpci_read16() argument
58 ret = dm_i2c_read(tcpci->dev, reg, buffer, 2); in tcpci_read16()
61 __func__, reg, ret); in tcpci_read16()
70 static int tcpci_block_read(struct tcpci *tcpci, unsigned int reg, in tcpci_block_read() argument
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c322 u32 reg, clock; in cm_get_main_vco_clk_hz() local
325 reg = readl(&clock_manager_base->main_pll.vco); in cm_get_main_vco_clk_hz()
327 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> in cm_get_main_vco_clk_hz()
329 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> in cm_get_main_vco_clk_hz()
337 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
340 reg = readl(&clock_manager_base->per_pll.vco); in cm_get_per_vco_clk_hz()
341 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> in cm_get_per_vco_clk_hz()
343 if (reg == CLKMGR_VCO_SSRC_EOSC1) in cm_get_per_vco_clk_hz()
345 else if (reg == CLKMGR_VCO_SSRC_EOSC2) in cm_get_per_vco_clk_hz()
347 else if (reg == CLKMGR_VCO_SSRC_F2S) in cm_get_per_vco_clk_hz()
[all …]
/rk3399_rockchip-uboot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3576.c19 int reg, ret, mask; in rk3576_set_mux() local
26 reg = bank->iomux[iomux_num].offset; in rk3576_set_mux()
28 reg += 0x4; in rk3576_set_mux()
36 reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ in rk3576_set_mux()
38 debug("iomux write reg = %x data = %x\n", reg, data); in rk3576_set_mux()
40 ret = regmap_write(regmap, reg, data); in rk3576_set_mux()
58 int *reg, u8 *bit) in rk3576_calc_drv_reg_and_bit() argument
64 *reg = RK3576_DRV_GPIO0_AL_OFFSET; in rk3576_calc_drv_reg_and_bit()
66 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; in rk3576_calc_drv_reg_and_bit()
68 *reg = RK3576_DRV_GPIO1_OFFSET; in rk3576_calc_drv_reg_and_bit()
[all …]
H A Dpinctrl-rv1108.c18 .reg = 0x418,
24 .reg = 0x418,
30 .reg = 0x418,
36 .reg = 0x418,
42 .reg = 0x418,
48 .reg = 0x418,
54 .reg = 0x418,
60 .reg = 0x418,
66 .reg = 0x41c,
72 .reg = 0x41c,
[all …]
H A Dpinctrl-rk3528.c19 int reg, ret, mask; in rk3528_set_mux() local
26 reg = bank->iomux[iomux_num].offset; in rk3528_set_mux()
28 reg += 0x4; in rk3528_set_mux()
35 debug("iomux write reg = %x data = %x\n", reg, data); in rk3528_set_mux()
37 ret = regmap_write(regmap, reg, data); in rk3528_set_mux()
52 int *reg, u8 *bit) in rk3528_calc_drv_reg_and_bit() argument
59 *reg = RK3528_DRV_GPIO0_OFFSET; in rk3528_calc_drv_reg_and_bit()
63 *reg = RK3528_DRV_GPIO1_OFFSET; in rk3528_calc_drv_reg_and_bit()
67 *reg = RK3528_DRV_GPIO2_OFFSET; in rk3528_calc_drv_reg_and_bit()
71 *reg = RK3528_DRV_GPIO3_OFFSET; in rk3528_calc_drv_reg_and_bit()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dmisc.c19 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned in mxs_wait_mask_set() argument
23 if ((readl(&reg->reg) & mask) == mask) in mxs_wait_mask_set()
31 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned in mxs_wait_mask_clr() argument
35 if ((readl(&reg->reg) & mask) == 0) in mxs_wait_mask_clr()
43 int mxs_reset_block(struct mxs_register_32 *reg) in mxs_reset_block() argument
46 writel(MXS_BLOCK_SFTRST, &reg->reg_clr); in mxs_reset_block()
48 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) in mxs_reset_block()
52 writel(MXS_BLOCK_CLKGATE, &reg->reg_clr); in mxs_reset_block()
55 writel(MXS_BLOCK_SFTRST, &reg->reg_set); in mxs_reset_block()
58 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) in mxs_reset_block()
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Dipu_disp.c184 u32 reg; in ipu_di_data_wave_config() local
185 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | in ipu_di_data_wave_config()
187 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
193 u32 reg; in ipu_di_data_pin_config() local
195 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
196 reg &= ~(0x3 << (di_pin * 2)); in ipu_di_data_pin_config()
197 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
198 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
212 u32 reg; in ipu_di_sync_config() local
221 reg = (run_count << 19) | (++run_src << 16) | in ipu_di_sync_config()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c37 static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) in da850_pll_init() argument
39 if (reg == davinci_pllc0_regs) in da850_pll_init()
47 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC); in da850_pll_init()
49 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC); in da850_pll_init()
52 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
56 if (reg == davinci_pllc0_regs) { in da850_pll_init()
61 dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9); in da850_pll_init()
62 setbits_le32(&reg->pllctl, in da850_pll_init()
67 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
70 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
[all …]
/rk3399_rockchip-uboot/board/freescale/ls1043aqds/
H A Dls1043aqds.c174 u8 reg; in board_retimer_init() local
178 reg = I2C_MUX_CH5; in board_retimer_init()
179 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1); in board_retimer_init()
182 reg = 0x0; in board_retimer_init()
183 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); in board_retimer_init()
186 i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1); in board_retimer_init()
187 debug("Retimer version id = 0x%x\n", reg); in board_retimer_init()
190 reg = 0x0c; in board_retimer_init()
191 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1); in board_retimer_init()
194 i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1); in board_retimer_init()
[all …]
/rk3399_rockchip-uboot/arch/x86/cpu/quark/
H A Dmsg_port.c12 void msg_port_setup(int op, int port, int reg) in msg_port_setup() argument
16 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); in msg_port_setup()
19 u32 msg_port_read(u8 port, u32 reg) in msg_port_read() argument
24 reg & 0xffffff00); in msg_port_read()
25 msg_port_setup(MSG_OP_READ, port, reg); in msg_port_read()
31 void msg_port_write(u8 port, u32 reg, u32 value) in msg_port_write() argument
35 reg & 0xffffff00); in msg_port_write()
36 msg_port_setup(MSG_OP_WRITE, port, reg); in msg_port_write()
39 u32 msg_port_alt_read(u8 port, u32 reg) in msg_port_alt_read() argument
44 reg & 0xffffff00); in msg_port_alt_read()
[all …]

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