Lines Matching refs:reg
184 u32 reg; in ipu_di_data_wave_config() local
185 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | in ipu_di_data_wave_config()
187 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_wave_config()
193 u32 reg; in ipu_di_data_pin_config() local
195 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
196 reg &= ~(0x3 << (di_pin * 2)); in ipu_di_data_pin_config()
197 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
198 __raw_writel(reg, DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
212 u32 reg; in ipu_di_sync_config() local
221 reg = (run_count << 19) | (++run_src << 16) | in ipu_di_sync_config()
223 __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); in ipu_di_sync_config()
224 reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | in ipu_di_sync_config()
226 reg |= (cnt_down << 16) | cnt_up; in ipu_di_sync_config()
229 reg |= 0x10000000; in ipu_di_sync_config()
231 __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); in ipu_di_sync_config()
232 reg = __raw_readl(DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
233 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); in ipu_di_sync_config()
234 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); in ipu_di_sync_config()
235 __raw_writel(reg, DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
241 u32 reg; in ipu_dc_map_config() local
243 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
244 reg &= ~(0xFFFF << (16 * (ptr & 0x1))); in ipu_dc_map_config()
245 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); in ipu_dc_map_config()
246 __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
248 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
249 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); in ipu_dc_map_config()
250 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); in ipu_dc_map_config()
251 __raw_writel(reg, DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
256 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_clear() local
257 __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), in ipu_dc_map_clear()
264 u32 reg; in ipu_dc_write_tmpl() local
267 reg = sync; in ipu_dc_write_tmpl()
268 reg |= (glue << 4); in ipu_dc_write_tmpl()
269 reg |= (++wave << 11); in ipu_dc_write_tmpl()
270 reg |= (++map << 15); in ipu_dc_write_tmpl()
271 reg |= (operand << 20) & 0xFFF00000; in ipu_dc_write_tmpl()
272 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); in ipu_dc_write_tmpl()
274 reg = (operand >> 12); in ipu_dc_write_tmpl()
275 reg |= opcode << 4; in ipu_dc_write_tmpl()
276 reg |= (stop << 9); in ipu_dc_write_tmpl()
277 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); in ipu_dc_write_tmpl()
282 u32 reg; in ipu_dc_link_event() local
284 reg = __raw_readl(DC_RL_CH(chan, event)); in ipu_dc_link_event()
285 reg &= ~(0xFFFF << (16 * (event & 0x1))); in ipu_dc_link_event()
286 reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); in ipu_dc_link_event()
287 __raw_writel(reg, DC_RL_CH(chan, event)); in ipu_dc_link_event()
383 u32 reg; in ipu_dp_csc_setup() local
387 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_csc_setup()
388 reg &= ~DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_csc_setup()
389 reg |= dp_csc_param.mode; in ipu_dp_csc_setup()
390 __raw_writel(reg, DP_COM_CONF()); in ipu_dp_csc_setup()
413 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_csc_setup()
414 __raw_writel(reg, IPU_SRM_PRI2); in ipu_dp_csc_setup()
424 uint32_t reg; in ipu_dp_init() local
469 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_init()
470 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && in ipu_dp_init()
492 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; in ipu_dp_init()
493 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); in ipu_dp_init()
533 u32 reg = 0; in ipu_dc_init() local
560 reg = 0x2; in ipu_dc_init()
561 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; in ipu_dc_init()
562 reg |= di << 2; in ipu_dc_init()
564 reg |= DC_WR_CH_CONF_FIELD_MODE; in ipu_dc_init()
570 reg = 0x3; in ipu_dc_init()
571 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; in ipu_dc_init()
573 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dc_init()
611 uint32_t reg; in ipu_dp_dc_enable() local
623 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_dc_enable()
624 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF()); in ipu_dp_dc_enable()
626 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_dc_enable()
627 __raw_writel(reg, IPU_SRM_PRI2); in ipu_dp_dc_enable()
634 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
635 if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { in ipu_dp_dc_enable()
636 reg &= ~DC_WR_CH_CONF_PROG_DI_ID; in ipu_dp_dc_enable()
637 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; in ipu_dp_dc_enable()
638 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_enable()
641 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_enable()
642 reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; in ipu_dp_dc_enable()
643 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_enable()
652 uint32_t reg; in ipu_dp_dc_disable() local
670 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_dc_disable()
671 csc = reg & DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_dc_disable()
673 reg &= ~DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_dc_disable()
675 reg &= ~DP_COM_CONF_FG_EN; in ipu_dp_dc_disable()
676 __raw_writel(reg, DP_COM_CONF()); in ipu_dp_dc_disable()
678 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_dc_disable()
679 __raw_writel(reg, IPU_SRM_PRI2); in ipu_dp_dc_disable()
710 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
711 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); in ipu_dp_dc_disable()
712 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; in ipu_dp_dc_disable()
713 reg ^= DC_WR_CH_CONF_PROG_DI_ID; in ipu_dp_dc_disable()
714 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
719 reg = __raw_readl(IPUIRQ_2_STATREG(irq)); in ipu_dp_dc_disable()
720 } while (!(reg & IPUIRQ_2_MASK(irq))); in ipu_dp_dc_disable()
722 reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
723 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; in ipu_dp_dc_disable()
724 __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); in ipu_dp_dc_disable()
726 reg = __raw_readl(IPU_DISP_GEN); in ipu_dp_dc_disable()
728 reg &= ~DI1_COUNTER_RELEASE; in ipu_dp_dc_disable()
730 reg &= ~DI0_COUNTER_RELEASE; in ipu_dp_dc_disable()
731 __raw_writel(reg, IPU_DISP_GEN); in ipu_dp_dc_disable()
836 uint32_t reg; in ipu_init_sync_panel() local
1064 reg = __raw_readl(DI_SW_GEN1(disp, 9)); in ipu_init_sync_panel()
1065 reg &= 0x1FFFFFFF; in ipu_init_sync_panel()
1066 reg |= (3 - 1)<<29 | 0x00008000; in ipu_init_sync_panel()
1067 __raw_writel(reg, DI_SW_GEN1(disp, 9)); in ipu_init_sync_panel()
1116 reg = __raw_readl(DI_STP_REP(disp, 6)); in ipu_init_sync_panel()
1117 reg &= 0x0000FFFF; in ipu_init_sync_panel()
1118 __raw_writel(reg, DI_STP_REP(disp, 6)); in ipu_init_sync_panel()
1148 reg = __raw_readl(DI_POL(disp)); in ipu_init_sync_panel()
1149 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); in ipu_init_sync_panel()
1151 reg |= DI_POL_DRDY_POLARITY_15; in ipu_init_sync_panel()
1153 reg |= DI_POL_DRDY_DATA_POLARITY; in ipu_init_sync_panel()
1154 __raw_writel(reg, DI_POL(disp)); in ipu_init_sync_panel()
1178 uint32_t reg; in ipu_disp_set_global_alpha() local
1197 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_global_alpha()
1198 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF()); in ipu_disp_set_global_alpha()
1200 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_global_alpha()
1201 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF()); in ipu_disp_set_global_alpha()
1205 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL; in ipu_disp_set_global_alpha()
1206 __raw_writel(reg | ((uint32_t) alpha << 24), in ipu_disp_set_global_alpha()
1209 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_global_alpha()
1210 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF()); in ipu_disp_set_global_alpha()
1212 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_global_alpha()
1213 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF()); in ipu_disp_set_global_alpha()
1216 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_disp_set_global_alpha()
1217 __raw_writel(reg, IPU_SRM_PRI2); in ipu_disp_set_global_alpha()
1239 uint32_t reg; in ipu_disp_set_color_key() local
1275 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; in ipu_disp_set_color_key()
1276 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); in ipu_disp_set_color_key()
1278 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_color_key()
1279 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF()); in ipu_disp_set_color_key()
1281 reg = __raw_readl(DP_COM_CONF()); in ipu_disp_set_color_key()
1282 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF()); in ipu_disp_set_color_key()
1285 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_disp_set_color_key()
1286 __raw_writel(reg, IPU_SRM_PRI2); in ipu_disp_set_color_key()