Lines Matching refs:reg
188 unsigned int reg; in cadence_qspi_apb_controller_enable() local
189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
190 reg |= CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_enable()
191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
196 unsigned int reg; in cadence_qspi_apb_controller_disable() local
197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
198 reg &= ~CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_controller_disable()
199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
232 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
235 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
238 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS; in cadence_qspi_apb_readdata_capture()
240 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS; in cadence_qspi_apb_readdata_capture()
242 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK in cadence_qspi_apb_readdata_capture()
245 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK) in cadence_qspi_apb_readdata_capture()
248 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
256 unsigned int reg; in cadence_qspi_apb_config_baudrate_div() local
260 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
261 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); in cadence_qspi_apb_config_baudrate_div()
277 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); in cadence_qspi_apb_config_baudrate_div()
278 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
285 unsigned int reg; in cadence_qspi_apb_set_clk_mode() local
288 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
289 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
292 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
294 reg |= CQSPI_REG_CONFIG_CLK_PHA; in cadence_qspi_apb_set_clk_mode()
296 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
304 unsigned int reg; in cadence_qspi_apb_chipselect() local
311 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
314 reg |= CQSPI_REG_CONFIG_DECODE; in cadence_qspi_apb_chipselect()
316 reg &= ~CQSPI_REG_CONFIG_DECODE; in cadence_qspi_apb_chipselect()
326 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK in cadence_qspi_apb_chipselect()
328 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) in cadence_qspi_apb_chipselect()
330 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
343 unsigned int reg; in cadence_qspi_apb_delay() local
363 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) in cadence_qspi_apb_delay()
365 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) in cadence_qspi_apb_delay()
367 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) in cadence_qspi_apb_delay()
369 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) in cadence_qspi_apb_delay()
371 writel(reg, reg_base + CQSPI_REG_DELAY); in cadence_qspi_apb_delay()
378 unsigned reg; in cadence_qspi_apb_controller_init() local
383 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
385 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); in cadence_qspi_apb_controller_init()
386 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); in cadence_qspi_apb_controller_init()
387 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); in cadence_qspi_apb_controller_init()
388 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); in cadence_qspi_apb_controller_init()
389 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
404 unsigned int reg) in cadence_qspi_apb_exec_flash_cmd() argument
409 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
411 reg |= CQSPI_REG_CMDCTRL_EXECUTE; in cadence_qspi_apb_exec_flash_cmd()
412 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
415 reg = readl(reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
416 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0) in cadence_qspi_apb_exec_flash_cmd()
438 unsigned int reg; in cadence_qspi_apb_command_read() local
448 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; in cadence_qspi_apb_command_read()
450 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); in cadence_qspi_apb_command_read()
453 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cadence_qspi_apb_command_read()
455 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); in cadence_qspi_apb_command_read()
459 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); in cadence_qspi_apb_command_read()
463 memcpy(rxbuf, ®, read_len); in cadence_qspi_apb_command_read()
467 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); in cadence_qspi_apb_command_read()
470 memcpy(rxbuf, ®, read_len); in cadence_qspi_apb_command_read()
479 unsigned int reg = 0; in cadence_qspi_apb_command_write() local
490 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; in cadence_qspi_apb_command_write()
494 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); in cadence_qspi_apb_command_write()
496 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) in cadence_qspi_apb_command_write()
507 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); in cadence_qspi_apb_command_write()
508 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cadence_qspi_apb_command_write()
526 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); in cadence_qspi_apb_command_write()
533 unsigned int reg; in cadence_qspi_apb_indirect_read_setup() local
595 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_indirect_read_setup()
596 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; in cadence_qspi_apb_indirect_read_setup()
597 reg |= (addr_bytes - 1); in cadence_qspi_apb_indirect_read_setup()
598 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_indirect_read_setup()
604 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL); in cadence_qspi_get_rd_sram_level() local
605 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; in cadence_qspi_get_rd_sram_level()
606 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; in cadence_qspi_get_rd_sram_level()
612 u32 reg; in cadence_qspi_wait_for_data() local
615 reg = cadence_qspi_get_rd_sram_level(plat); in cadence_qspi_wait_for_data()
616 if (reg) in cadence_qspi_wait_for_data()
617 return reg; in cadence_qspi_wait_for_data()
690 unsigned int reg; in cadence_qspi_apb_indirect_write_setup() local
703 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; in cadence_qspi_apb_indirect_write_setup()
704 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); in cadence_qspi_apb_indirect_write_setup()
707 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); in cadence_qspi_apb_indirect_write_setup()
708 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); in cadence_qspi_apb_indirect_write_setup()
710 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_indirect_write_setup()
711 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; in cadence_qspi_apb_indirect_write_setup()
712 reg |= (addr_bytes - 1); in cadence_qspi_apb_indirect_write_setup()
713 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_indirect_write_setup()
774 unsigned int reg; in cadence_qspi_apb_enter_xip() local
777 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
778 reg |= CQSPI_REG_CONFIG_ENABLE; in cadence_qspi_apb_enter_xip()
779 reg |= CQSPI_REG_CONFIG_DIRECT; in cadence_qspi_apb_enter_xip()
780 reg |= CQSPI_REG_CONFIG_XIP_IMM; in cadence_qspi_apb_enter_xip()
781 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
787 reg = readl(reg_base + CQSPI_REG_RD_INSTR); in cadence_qspi_apb_enter_xip()
788 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); in cadence_qspi_apb_enter_xip()
789 writel(reg, reg_base + CQSPI_REG_RD_INSTR); in cadence_qspi_apb_enter_xip()