Lines Matching refs:reg
21 unsigned int reg; in exynos_mipi_dsi_func_reset() local
26 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
28 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
30 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_func_reset()
35 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
40 reg = readl(&mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
42 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
43 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_sw_reset()
45 writel(reg, &mipi_dsim->swrst); in exynos_mipi_dsi_sw_reset()
52 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
54 reg |= INTSRC_SWRST_RELEASE; in exynos_mipi_dsi_sw_release()
56 writel(reg, &mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release()
64 unsigned int reg = readl(&mipi_dsim->intmsk); in exynos_mipi_dsi_set_interrupt_mask() local
67 reg |= mode; in exynos_mipi_dsi_set_interrupt_mask()
69 reg &= ~mode; in exynos_mipi_dsi_set_interrupt_mask()
71 writel(reg, &mipi_dsim->intmsk); in exynos_mipi_dsi_set_interrupt_mask()
77 unsigned int reg; in exynos_mipi_dsi_init_fifo_pointer() local
81 reg = readl(&mipi_dsim->fifoctrl); in exynos_mipi_dsi_init_fifo_pointer()
83 writel(reg & ~(cfg), &mipi_dsim->fifoctrl); in exynos_mipi_dsi_init_fifo_pointer()
85 reg |= cfg; in exynos_mipi_dsi_init_fifo_pointer()
87 writel(reg, &mipi_dsim->fifoctrl); in exynos_mipi_dsi_init_fifo_pointer()
105 unsigned int reg; in exynos_mipi_dsi_set_main_disp_resol() local
110 reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); in exynos_mipi_dsi_set_main_disp_resol()
111 writel(reg, &mipi_dsim->mdresol); in exynos_mipi_dsi_set_main_disp_resol()
114 reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff)); in exynos_mipi_dsi_set_main_disp_resol()
115 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); in exynos_mipi_dsi_set_main_disp_resol()
117 reg |= DSIM_MAIN_STAND_BY; in exynos_mipi_dsi_set_main_disp_resol()
118 writel(reg, &mipi_dsim->mdresol); in exynos_mipi_dsi_set_main_disp_resol()
124 unsigned int reg; in exynos_mipi_dsi_set_main_disp_vporch() local
128 reg = (readl(&mipi_dsim->mvporch)) & in exynos_mipi_dsi_set_main_disp_vporch()
132 reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | in exynos_mipi_dsi_set_main_disp_vporch()
136 writel(reg, &mipi_dsim->mvporch); in exynos_mipi_dsi_set_main_disp_vporch()
142 unsigned int reg; in exynos_mipi_dsi_set_main_disp_hporch() local
146 reg = (readl(&mipi_dsim->mhporch)) & in exynos_mipi_dsi_set_main_disp_hporch()
149 reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); in exynos_mipi_dsi_set_main_disp_hporch()
151 writel(reg, &mipi_dsim->mhporch); in exynos_mipi_dsi_set_main_disp_hporch()
157 unsigned int reg; in exynos_mipi_dsi_set_main_disp_sync_area() local
161 reg = (readl(&mipi_dsim->msync)) & in exynos_mipi_dsi_set_main_disp_sync_area()
164 reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | in exynos_mipi_dsi_set_main_disp_sync_area()
167 writel(reg, &mipi_dsim->msync); in exynos_mipi_dsi_set_main_disp_sync_area()
173 unsigned int reg; in exynos_mipi_dsi_set_sub_disp_resol() local
177 reg = (readl(&mipi_dsim->sdresol)) & in exynos_mipi_dsi_set_sub_disp_resol()
180 writel(reg, &mipi_dsim->sdresol); in exynos_mipi_dsi_set_sub_disp_resol()
182 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); in exynos_mipi_dsi_set_sub_disp_resol()
183 reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | in exynos_mipi_dsi_set_sub_disp_resol()
185 writel(reg, &mipi_dsim->sdresol); in exynos_mipi_dsi_set_sub_disp_resol()
188 reg |= (1 << DSIM_SUB_STANDY_SHIFT); in exynos_mipi_dsi_set_sub_disp_resol()
189 writel(reg, &mipi_dsim->sdresol); in exynos_mipi_dsi_set_sub_disp_resol()
220 u32 reg = (readl(&mipi_dsim->config)) & in exynos_mipi_dsi_display_config() local
226 reg |= (1 << DSIM_VIDEO_MODE_SHIFT); in exynos_mipi_dsi_display_config()
228 reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT); in exynos_mipi_dsi_display_config()
235 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT in exynos_mipi_dsi_display_config()
239 writel(reg, &mipi_dsim->config); in exynos_mipi_dsi_display_config()
245 unsigned int reg; in exynos_mipi_dsi_enable_lane() local
249 reg = readl(&mipi_dsim->config); in exynos_mipi_dsi_enable_lane()
252 reg |= DSIM_LANE_ENx(lane); in exynos_mipi_dsi_enable_lane()
254 reg &= ~DSIM_LANE_ENx(lane); in exynos_mipi_dsi_enable_lane()
256 writel(reg, &mipi_dsim->config); in exynos_mipi_dsi_enable_lane()
277 unsigned int reg = readl(&mipi_dsim->phyacchr); in exynos_mipi_dsi_enable_afc() local
279 reg = 0; in exynos_mipi_dsi_enable_afc()
282 reg |= DSIM_AFC_EN; in exynos_mipi_dsi_enable_afc()
283 reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT); in exynos_mipi_dsi_enable_afc()
284 reg |= DSIM_AFC_CTL(afc_code); in exynos_mipi_dsi_enable_afc()
286 reg &= ~DSIM_AFC_EN; in exynos_mipi_dsi_enable_afc()
288 writel(reg, &mipi_dsim->phyacchr); in exynos_mipi_dsi_enable_afc()
296 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & in exynos_mipi_dsi_enable_pll_bypass() local
299 reg |= enable << DSIM_PLL_BYPASS_SHIFT; in exynos_mipi_dsi_enable_pll_bypass()
301 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_enable_pll_bypass()
309 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & in exynos_mipi_dsi_pll_freq_band() local
312 reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); in exynos_mipi_dsi_pll_freq_band()
314 writel(reg, &mipi_dsim->pllctrl); in exynos_mipi_dsi_pll_freq_band()
323 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & in exynos_mipi_dsi_pll_freq() local
326 reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) | in exynos_mipi_dsi_pll_freq()
330 writel(reg, &mipi_dsim->pllctrl); in exynos_mipi_dsi_pll_freq()
347 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & in exynos_mipi_dsi_enable_pll() local
350 reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); in exynos_mipi_dsi_enable_pll()
352 writel(reg, &mipi_dsim->pllctrl); in exynos_mipi_dsi_enable_pll()
360 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & in exynos_mipi_dsi_set_byte_clock_src() local
363 reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; in exynos_mipi_dsi_set_byte_clock_src()
365 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_set_byte_clock_src()
373 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & in exynos_mipi_dsi_enable_byte_clock() local
376 reg |= enable << DSIM_BYTE_CLKEN_SHIFT; in exynos_mipi_dsi_enable_byte_clock()
378 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_enable_byte_clock()
386 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & in exynos_mipi_dsi_set_esc_clk_prs() local
389 reg |= enable << DSIM_ESC_CLKEN_SHIFT; in exynos_mipi_dsi_set_esc_clk_prs()
391 reg |= prs_val; in exynos_mipi_dsi_set_esc_clk_prs()
393 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_set_esc_clk_prs()
401 unsigned int reg = readl(&mipi_dsim->clkctrl); in exynos_mipi_dsi_enable_esc_clk_on_lane() local
404 reg |= DSIM_LANE_ESC_CLKEN(lane_sel); in exynos_mipi_dsi_enable_esc_clk_on_lane()
406 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); in exynos_mipi_dsi_enable_esc_clk_on_lane()
408 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_enable_esc_clk_on_lane()
416 unsigned int reg = (readl(&mipi_dsim->escmode)) & in exynos_mipi_dsi_force_dphy_stop_state() local
419 reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); in exynos_mipi_dsi_force_dphy_stop_state()
421 writel(reg, &mipi_dsim->escmode); in exynos_mipi_dsi_force_dphy_stop_state()
428 unsigned int reg = readl(&mipi_dsim->status); in exynos_mipi_dsi_is_lane_state() local
436 if ((reg & DSIM_STOP_STATE_DAT(0xf)) && in exynos_mipi_dsi_is_lane_state()
437 ((reg & DSIM_STOP_STATE_CLK) || in exynos_mipi_dsi_is_lane_state()
438 (reg & DSIM_TX_READY_HS_CLK))) in exynos_mipi_dsi_is_lane_state()
449 unsigned int reg = (readl(&mipi_dsim->escmode)) & in exynos_mipi_dsi_set_stop_state_counter() local
452 reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); in exynos_mipi_dsi_set_stop_state_counter()
454 writel(reg, &mipi_dsim->escmode); in exynos_mipi_dsi_set_stop_state_counter()
462 unsigned int reg = (readl(&mipi_dsim->timeout)) & in exynos_mipi_dsi_set_bta_timeout() local
465 reg |= (timeout << DSIM_BTA_TOUT_SHIFT); in exynos_mipi_dsi_set_bta_timeout()
467 writel(reg, &mipi_dsim->timeout); in exynos_mipi_dsi_set_bta_timeout()
475 unsigned int reg = (readl(&mipi_dsim->timeout)) & in exynos_mipi_dsi_set_lpdr_timeout() local
478 reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); in exynos_mipi_dsi_set_lpdr_timeout()
480 writel(reg, &mipi_dsim->timeout); in exynos_mipi_dsi_set_lpdr_timeout()
488 unsigned int reg = readl(&mipi_dsim->escmode); in exynos_mipi_dsi_set_cpu_transfer_mode() local
490 reg &= ~DSIM_CMD_LPDT_LP; in exynos_mipi_dsi_set_cpu_transfer_mode()
493 reg |= DSIM_CMD_LPDT_LP; in exynos_mipi_dsi_set_cpu_transfer_mode()
495 writel(reg, &mipi_dsim->escmode); in exynos_mipi_dsi_set_cpu_transfer_mode()
503 unsigned int reg = readl(&mipi_dsim->escmode); in exynos_mipi_dsi_set_lcdc_transfer_mode() local
505 reg &= ~DSIM_TX_LPDT_LP; in exynos_mipi_dsi_set_lcdc_transfer_mode()
508 reg |= DSIM_TX_LPDT_LP; in exynos_mipi_dsi_set_lcdc_transfer_mode()
510 writel(reg, &mipi_dsim->escmode); in exynos_mipi_dsi_set_lcdc_transfer_mode()
518 unsigned int reg = (readl(&mipi_dsim->clkctrl)) & in exynos_mipi_dsi_enable_hs_clock() local
521 reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; in exynos_mipi_dsi_enable_hs_clock()
523 writel(reg, &mipi_dsim->clkctrl); in exynos_mipi_dsi_enable_hs_clock()
531 unsigned int reg = readl(&mipi_dsim->phyacchr1); in exynos_mipi_dsi_dp_dn_swap() local
533 reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT); in exynos_mipi_dsi_dp_dn_swap()
534 reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT; in exynos_mipi_dsi_dp_dn_swap()
536 writel(reg, &mipi_dsim->phyacchr1); in exynos_mipi_dsi_dp_dn_swap()
544 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & in exynos_mipi_dsi_hs_zero_ctrl() local
547 reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT); in exynos_mipi_dsi_hs_zero_ctrl()
549 writel(reg, &mipi_dsim->pllctrl); in exynos_mipi_dsi_hs_zero_ctrl()
556 unsigned int reg = (readl(&mipi_dsim->pllctrl)) & in exynos_mipi_dsi_prep_ctrl() local
559 reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT); in exynos_mipi_dsi_prep_ctrl()
561 writel(reg, &mipi_dsim->pllctrl); in exynos_mipi_dsi_prep_ctrl()
568 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_clear_interrupt() local
570 reg |= INTSRC_PLL_STABLE; in exynos_mipi_dsi_clear_interrupt()
572 writel(reg, &mipi_dsim->intsrc); in exynos_mipi_dsi_clear_interrupt()
585 unsigned int reg; in exynos_mipi_dsi_is_pll_stable() local
589 reg = readl(&mipi_dsim->status); in exynos_mipi_dsi_is_pll_stable()
591 return reg & DSIM_PLL_STABLE ? 1 : 0; in exynos_mipi_dsi_is_pll_stable()
607 unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) | in exynos_mipi_dsi_wr_tx_header() local
610 writel(reg, &mipi_dsim->pkthdr); in exynos_mipi_dsi_wr_tx_header()
618 unsigned int reg = readl(&mipi_dsim->intsrc); in _exynos_mipi_dsi_get_frame_done_status() local
620 return (reg & INTSRC_FRAME_DONE) ? 1 : 0; in _exynos_mipi_dsi_get_frame_done_status()
627 unsigned int reg = readl(&mipi_dsim->intsrc); in _exynos_mipi_dsi_clear_frame_done() local
629 writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc); in _exynos_mipi_dsi_clear_frame_done()