35 	u32 reg;  in wb_start()  local
43 		: "=r"(reg)		/* output */  in wb_start()
47 	if (reg != NV_WB_RUN_ADDRESS)  in wb_start()
56 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
57 	reg |= SWR_CSITE_RST;  in wb_start()
58 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
69 		reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;  in wb_start()
70 		writel(reg, &pmc->pmc_pwrgate_toggle);  in wb_start()
76 	reg = readl(&pmc->pmc_remove_clamping);  in wb_start()
77 	reg |= CPU_CLMP;  in wb_start()
78 	writel(reg, &pmc->pmc_remove_clamping);  in wb_start()
80 	reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;  in wb_start()
81 	writel(reg, &flow->halt_cop_events);  in wb_start()
84 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
85 	reg |= CPU_RST;  in wb_start()
86 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
89 	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |  in wb_start()
91 	writel(reg, &clkrst->crc_cpu_cmplx_set);  in wb_start()
100 	reg = readl(&pmc->pmc_scratch41);  in wb_start()
101 	writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);  in wb_start()
107 	reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |  in wb_start()
109 	writel(reg, &clkrst->crc_clk_cpu_cmplx);  in wb_start()
112 	reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
113 	reg |= CLK_ENB_CPU;  in wb_start()
114 	writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
117 	reg = readl(TIMER_USEC_CNTR);  in wb_start()
118 	while (readl(TIMER_USEC_CNTR) <= (reg + 2))  in wb_start()
128 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
129 	reg &= ~SWR_CSITE_RST;  in wb_start()
130 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
134 	reg = 0xC5ACCE55;  in wb_start()
135 	writel(reg, CSITE_CPU_DBG0_LAR);  in wb_start()
136 	writel(reg, CSITE_CPU_DBG1_LAR);  in wb_start()
142 	reg = readl(TIMER_USEC_CNTR);  in wb_start()
143 	writel(reg, &pmc->pmc_scratch1);  in wb_start()
150 	reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;  in wb_start()
159 	if (reg > 26)  in wb_start()
160 		reg = 19;  in wb_start()
163 	if (scratch3.pllx_base_divm == reg)  in wb_start()
164 		reg = 0;  in wb_start()
166 		reg = 1;  in wb_start()
170 	reg = scratch3.pllx_base_divn << reg;  in wb_start()
174 	reg = reg >> scratch3.pllx_base_divp;  in wb_start()
179 	if (reg > 600)  in wb_start()
198 	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;  in wb_start()
199 	writel(reg, &clkrst->crc_cpu_cmplx_clr);  in wb_start()
201 	reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |  in wb_start()
203 	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);  in wb_start()
205 	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |  in wb_start()
208 	writel(reg, &clkrst->crc_sclk_brst_pol);  in wb_start()
211 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
212 	reg &= ~CPU_RST;  in wb_start()
213 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
217 	reg = EVENT_MODE_STOP | EVENT_JTAG;  in wb_start()
218 	writel(reg, flow->halt_cop_events);  in wb_start()