video/drm: analogix_dp: add support for ASSR mode

According to the eDP v1.3 chapter 3.6 Table 3-15, Alternative
Scramble Seed Reset(ASSR) is a recommended way for eDP Sink devices
to support Display

video/drm: analogix_dp: add support for ASSR mode

According to the eDP v1.3 chapter 3.6 Table 3-15, Alternative
Scramble Seed Reset(ASSR) is a recommended way for eDP Sink devices
to support Display Authentication and Content Protection as Method
3a, while Method 1 HDCP is normally not expected in an eDP Sink
device.

In addition, the ASSR support capability should be the bit 0 of
DPCD register 0000Dh according to the eDP v1.4 'Revision History'
table 2:

......
Table 3-4: Corrected reference to DPCD Address 0000Dh, bit 0 (was bit 4)
......

Change-Id: I311a8ed0baae37047e84bdc697842c5bb3fcd6fb
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: read/write DPCD through drm_dp_aux

Sync the functions of DPCD read/write with Kernel:

analogix_dp_write_byte_to_dpcd() -> drm_dp_dpcd_writeb()
analogix_dp_read_byte_from_dpc

video/drm: analogix_dp: read/write DPCD through drm_dp_aux

Sync the functions of DPCD read/write with Kernel:

analogix_dp_write_byte_to_dpcd() -> drm_dp_dpcd_writeb()
analogix_dp_read_byte_from_dpcd() -> drm_dp_dpcd_readb()
analogix_dp_write_bytes_to_dpcd() -> drm_dp_dpcd_write()
analogix_dp_read_bytes_from_dpcd() -> drm_dp_dpcd_read()

In addition, the older functions may not have the return value check.
So the necessary return value check have been added in the patch, which
is also synchronized with Kernel.

With the patch, the analogix_dp driver will be more maintainable and
readable.

Change-Id: Ic2b7d6d9ab32ecec0c5bb6de09082c536cae1a41
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

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video/drm: analogix_dp: register drm_dp_aux and support the transfer function of aux

Change-Id: Iccb0a170d73fe6e7960ca759015b38bd5c9d70da
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>

Revert "video/drm: analogix_dp: Fix sync polarity configuration in msa packet"

This reverts commit 57c33e2a3cb453933624c3769fe2f65158030c38.

VOP only supports the negative polarity of vsync/hsync o

Revert "video/drm: analogix_dp: Fix sync polarity configuration in msa packet"

This reverts commit 57c33e2a3cb453933624c3769fe2f65158030c38.

VOP only supports the negative polarity of vsync/hsync on rk3588.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If830138671b6a47bacbff0af7357457a974d5abd

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video/drm: analogix_dp: Fix stream valid control

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id

video/drm: analogix_dp: Fix stream valid control

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I94c32572bc8b58cc5902a1ada23f45f300d06ca5

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video/drm: analogix_dp: Fix sync polarity configuration in msa packet

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock

video/drm: analogix_dp: Fix sync polarity configuration in msa packet

Fixes: e9cac7f1fea9 ("video/drm: analogix_dp: Use video format information from register")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I3cbf36d59976e460a852c16b039393311da69e18

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video/drm: analogix_dp: Use video format information from register

Force sync polarity to active low for RK3588.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I73270addc6118279accf6d9

video/drm: analogix_dp: Use video format information from register

Force sync polarity to active low for RK3588.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I73270addc6118279accf6d9ba01f3f018a4e0850

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video/drm: analogix_dp: Support DT specified physical-logical lane mappings

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ic61ba6f12b24f4179441430794c7641c9cd6753e

video/drm: analogix_dp: support video BIST generation

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I4e17a0215f6114e3cb02867e6800ab060f384ca7

video/drm: analogix_dp: Set link power state

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I69e08c0d010dfc94e375c9c107abe9e14d7f4b70

video/drm: analogix_dp: Add support for rk3588

Change-Id: I4cbfc252fefa6819e74d74e59ffd4ab7494f4001
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

video/drm: analogix_dp: Fix display corruption in low temperature environment

Change-Id: I2b2bbbd93d0f7b315afefa14720acab5ccd31c6d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

video/drm: analogix_dp: Fix voltage_swing/pre_emphasis level calculation

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I07a071b77a254cbe940b4df4dd6b52b069339076

video/drm: analogix_dp: Add support for rk3568

This patch adds support for Analogix eDP TX IP used on RK3568 SoC.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba

video/drm: analogix_dp: Add support for rk3568

This patch adds support for Analogix eDP TX IP used on RK3568 SoC.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ia48f1f99f336d4d98d5fba4e5fd15a35bdbaf373

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video/drm: analogix_dp: Move PLL lock check to analogix_dp_set_link_bandwidth()

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iffd2ff42de9102cf0293cf7bb68422dd6331474b

video/drm: analogix_dp: Simplify analogix_dp_{set/get}_lane_link_training helpers

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5e0a90c8a1fd132567635a7751c1ca4ade38e692

video/drm: analogix_dp: Implement detect callback

Change-Id: I1e6746768092747920afcb3af07e36c1ecae9856
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

Merge branch 'next-dev' into thunder-boot

video/drm: analogix_dp: Workaround async issue between pclk clock and 24m clock

Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need

video/drm: analogix_dp: Workaround async issue between pclk clock and 24m clock

Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need to go through EDP APB
read/write bus and EDP internal read/write bus;
- EDP APB read/write bus is on the EDP pclk clock domain;
- EDP internal read/write bus is on the EDP 24m clock domain;
- Asynchronous logic circuit is added between APB read/write bus and
Internal read/write bus;

Issue:
There is a bug on the Asynchronous logic circuit between APB read/write
bus and Internal read/write bus; This bug will be random to cause the
following wrong control/address signals sequence happen;
- For write, maybe wrong register address is wrote in;
- For read, maybe wrong register address is read out;

Workaround:
- For CPU write EDP register operation, write any register need
following three steps,
1): Read EDP_BASE+0x00 dummy register firstly, latch the dummy
register address on Reg_Address bus, to avoid next step write to
wrong register to cause function register overrun;
2): 1st time to write the EDP register you want to operate,
to latch the real write address on Reg_Address bus;
3): 2nd time to write the EDP register you want to operate,
to make sure the data is write on the real write address;
- For CPU read EDP register operation, read any register need following
two steps,
1): 1st time to read the EDP register you want to operate, to latch
the real read address on Reg_Address bus;
2): 2nd time to read the EDP register you want to operate, to make
sure the data is read out from the real read address;

Change-Id: I42613145b1d414321ac1aef290a35969a1461e36
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

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video/drm: Rename rockchip_analogix_dp to analogix_dp

Change-Id: I5603a709abde6a852fcca0b3a5b833727d5f3cad
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>