1faa83232SBin Meng /*
2faa83232SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3faa83232SBin Meng *
4faa83232SBin Meng * SPDX-License-Identifier: GPL-2.0+
5faa83232SBin Meng */
6faa83232SBin Meng
7faa83232SBin Meng #include <common.h>
8faa83232SBin Meng #include <asm/arch/device.h>
9faa83232SBin Meng #include <asm/arch/msg_port.h>
10*5750e5e2SBin Meng #include <asm/arch/quark.h>
11faa83232SBin Meng
msg_port_setup(int op,int port,int reg)12faa83232SBin Meng void msg_port_setup(int op, int port, int reg)
13faa83232SBin Meng {
14*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
15faa83232SBin Meng (((op) << 24) | ((port) << 16) |
16faa83232SBin Meng (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
17faa83232SBin Meng }
18faa83232SBin Meng
msg_port_read(u8 port,u32 reg)19faa83232SBin Meng u32 msg_port_read(u8 port, u32 reg)
20faa83232SBin Meng {
21faa83232SBin Meng u32 value;
22faa83232SBin Meng
23*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
24faa83232SBin Meng reg & 0xffffff00);
25faa83232SBin Meng msg_port_setup(MSG_OP_READ, port, reg);
26*5750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
27faa83232SBin Meng
28faa83232SBin Meng return value;
29faa83232SBin Meng }
30faa83232SBin Meng
msg_port_write(u8 port,u32 reg,u32 value)31faa83232SBin Meng void msg_port_write(u8 port, u32 reg, u32 value)
32faa83232SBin Meng {
33*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
34*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
35faa83232SBin Meng reg & 0xffffff00);
36faa83232SBin Meng msg_port_setup(MSG_OP_WRITE, port, reg);
37faa83232SBin Meng }
38faa83232SBin Meng
msg_port_alt_read(u8 port,u32 reg)39faa83232SBin Meng u32 msg_port_alt_read(u8 port, u32 reg)
40faa83232SBin Meng {
41faa83232SBin Meng u32 value;
42faa83232SBin Meng
43*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
44faa83232SBin Meng reg & 0xffffff00);
45faa83232SBin Meng msg_port_setup(MSG_OP_ALT_READ, port, reg);
46*5750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
47faa83232SBin Meng
48faa83232SBin Meng return value;
49faa83232SBin Meng }
50faa83232SBin Meng
msg_port_alt_write(u8 port,u32 reg,u32 value)51faa83232SBin Meng void msg_port_alt_write(u8 port, u32 reg, u32 value)
52faa83232SBin Meng {
53*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
54*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
55faa83232SBin Meng reg & 0xffffff00);
56faa83232SBin Meng msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
57faa83232SBin Meng }
58faa83232SBin Meng
msg_port_io_read(u8 port,u32 reg)59faa83232SBin Meng u32 msg_port_io_read(u8 port, u32 reg)
60faa83232SBin Meng {
61faa83232SBin Meng u32 value;
62faa83232SBin Meng
63*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
64faa83232SBin Meng reg & 0xffffff00);
65faa83232SBin Meng msg_port_setup(MSG_OP_IO_READ, port, reg);
66*5750e5e2SBin Meng qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
67faa83232SBin Meng
68faa83232SBin Meng return value;
69faa83232SBin Meng }
70faa83232SBin Meng
msg_port_io_write(u8 port,u32 reg,u32 value)71faa83232SBin Meng void msg_port_io_write(u8 port, u32 reg, u32 value)
72faa83232SBin Meng {
73*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
74*5750e5e2SBin Meng qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
75faa83232SBin Meng reg & 0xffffff00);
76faa83232SBin Meng msg_port_setup(MSG_OP_IO_WRITE, port, reg);
77faa83232SBin Meng }
78