322 	u32 reg, clock;  in cm_get_main_vco_clk_hz()  local
325 	reg = readl(&clock_manager_base->main_pll.vco);  in cm_get_main_vco_clk_hz()
327 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>  in cm_get_main_vco_clk_hz()
329 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>  in cm_get_main_vco_clk_hz()
337 	u32 reg, clock = 0;  in cm_get_per_vco_clk_hz()  local
340 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
341 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>  in cm_get_per_vco_clk_hz()
343 	if (reg == CLKMGR_VCO_SSRC_EOSC1)  in cm_get_per_vco_clk_hz()
345 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)  in cm_get_per_vco_clk_hz()
347 	else if (reg == CLKMGR_VCO_SSRC_F2S)  in cm_get_per_vco_clk_hz()
351 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
352 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>  in cm_get_per_vco_clk_hz()
354 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>  in cm_get_per_vco_clk_hz()
362 	u32 reg, clock;  in cm_get_mpu_clk_hz()  local
367 	reg = readl(&clock_manager_base->altera.mpuclk);  in cm_get_mpu_clk_hz()
368 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
369 	reg = readl(&clock_manager_base->main_pll.mpuclk);  in cm_get_mpu_clk_hz()
370 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
376 	u32 reg, clock = 0;  in cm_get_sdram_clk_hz()  local
379 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()
380 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>  in cm_get_sdram_clk_hz()
382 	if (reg == CLKMGR_VCO_SSRC_EOSC1)  in cm_get_sdram_clk_hz()
384 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)  in cm_get_sdram_clk_hz()
386 	else if (reg == CLKMGR_VCO_SSRC_F2S)  in cm_get_sdram_clk_hz()
390 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()
391 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>  in cm_get_sdram_clk_hz()
393 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>  in cm_get_sdram_clk_hz()
397 	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);  in cm_get_sdram_clk_hz()
398 	reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>  in cm_get_sdram_clk_hz()
400 	clock /= (reg + 1);  in cm_get_sdram_clk_hz()
407 	u32 reg, clock = 0;  in cm_get_l4_sp_clk_hz()  local
410 	reg = readl(&clock_manager_base->main_pll.l4src);  in cm_get_l4_sp_clk_hz()
411 	reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>  in cm_get_l4_sp_clk_hz()
414 	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {  in cm_get_l4_sp_clk_hz()
418 		reg = readl(&clock_manager_base->altera.mainclk);  in cm_get_l4_sp_clk_hz()
419 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
420 		reg = readl(&clock_manager_base->main_pll.mainclk);  in cm_get_l4_sp_clk_hz()
421 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
422 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {  in cm_get_l4_sp_clk_hz()
426 		reg = readl(&clock_manager_base->per_pll.perbaseclk);  in cm_get_l4_sp_clk_hz()
427 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
431 	reg = readl(&clock_manager_base->main_pll.maindiv);  in cm_get_l4_sp_clk_hz()
432 	reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>  in cm_get_l4_sp_clk_hz()
434 	clock = clock / (1 << reg);  in cm_get_l4_sp_clk_hz()
441 	u32 reg, clock = 0;  in cm_get_mmc_controller_clk_hz()  local
444 	reg = readl(&clock_manager_base->per_pll.src);  in cm_get_mmc_controller_clk_hz()
445 	reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>  in cm_get_mmc_controller_clk_hz()
448 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {  in cm_get_mmc_controller_clk_hz()
450 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {  in cm_get_mmc_controller_clk_hz()
454 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);  in cm_get_mmc_controller_clk_hz()
455 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
456 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {  in cm_get_mmc_controller_clk_hz()
460 		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);  in cm_get_mmc_controller_clk_hz()
461 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
471 	u32 reg, clock = 0;  in cm_get_qspi_controller_clk_hz()  local
474 	reg = readl(&clock_manager_base->per_pll.src);  in cm_get_qspi_controller_clk_hz()
475 	reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>  in cm_get_qspi_controller_clk_hz()
478 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {  in cm_get_qspi_controller_clk_hz()
480 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {  in cm_get_qspi_controller_clk_hz()
484 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);  in cm_get_qspi_controller_clk_hz()
485 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
486 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {  in cm_get_qspi_controller_clk_hz()
490 		reg = readl(&clock_manager_base->per_pll.perqspiclk);  in cm_get_qspi_controller_clk_hz()
491 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
499 	u32 reg, clock = 0;  in cm_get_spi_controller_clk_hz()  local
504 	reg = readl(&clock_manager_base->per_pll.perbaseclk);  in cm_get_spi_controller_clk_hz()
505 	clock /= (reg + 1);  in cm_get_spi_controller_clk_hz()