UPSTREAM: Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.

Using bounce_buf.c to handle non-DMA alig

UPSTREAM: Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"

This reverts commit 57897c13de03ac0136d64641a3eab526c6810387.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
(cherry picked from commit a743e2ba3837db5e8499b03f0f57c3610d03a570)
Change-Id: I793c697ad11d10259e233b2a6b0fe6e6f0b3df85
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.

This commit changed cadence_qspi_apb to us

UPSTREAM: Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"

This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Change-Id: If32c692ac37cf2ee25254b7ecc49bc09096bf5d0
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 948ad4f07598a729a0de523ed3d779115b2fa2f2)

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UPSTREAM: spi: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong

UPSTREAM: spi: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Change-Id: Ic221ac76abf1a32a027b9650bc6f27667209c77c
Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 15a70a5da33229de884f60684a562ea60fe505b2)

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UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwie

UPSTREAM: wait_bit: use wait_for_bit_le32 and remove wait_for_bit

wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Change-Id: I638846de7db29711fb7c778cc8304b507de057fe
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 48263504c8d501678acaa90c075f3f7cda17c316)
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-spi

spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible

According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted

spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible

According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitte

spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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Merge branch 'master' of git://git.denx.de/u-boot-spi

spi: cadence_qspi: Fix CS timings

The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads

spi: cadence_qspi: Fix CS timings

The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.

In addition, the existing code does not handle the case when the delay
is less than a SCLK period.

This change accurately calculates the additional delays in Ref clocks.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Remove returns from end of void functions

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@ope

spi: cadence_qspi: Remove returns from end of void functions

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Use spi mode at the point it is needed

Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by:

spi: cadence_qspi: Use spi mode at the point it is needed

Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Clean up the #define names

A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remo

spi: cadence_qspi: Clean up the #define names

A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.

Whilst doing so, also remove the unnecessary brackets around the
constants.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Use #define for bits instead of bit shifts

Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
co

spi: cadence_qspi: Use #define for bits instead of bit shifts

Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.

Whislt at it, fix the names of the "Rd Data Capture" register defs.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Better debug information on the SPI clock rate

Show what the output clock rate actually is.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.

spi: cadence_qspi: Better debug information on the SPI clock rate

Show what the output clock rate actually is.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Fix baud rate calculation

With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32)

spi: cadence_qspi: Fix baud rate calculation

With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up the divider to generate
25MHz.

This change fixes the calculation.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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spi: cadence_qspi: Fix clearing of pol/pha bits

Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com

spi: cadence_qspi: Fix clearing of pol/pha bits

Or'ing together bit positions is clearly wrong.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

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treewide: replace #include <asm/errno.h> with <linux/errno.h>

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)

Replace

treewide: replace #include <asm/errno.h> with <linux/errno.h>

Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>

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spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value

Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
corre

spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value

Ensuring the baudrate divisor value doesn't exceed the max value
in the calculation.It will be capped at max value to ensure the
correct value being written into the register.

Example of the existing bug is when calculated div = 16. After and
with the mask, the value written to register is actually 0 (register
field for baudrate divisor). With this fix, the value written is now
15 which is max value for baudrate divisor.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Dinh Nguyen <dinguyen@altera.com>

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Merge branch 'master' of git://git.denx.de/u-boot-spi

spi: cadence_quadspi: Enable QUAD mode based on DT data

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine

spi: cadence_quadspi: Enable QUAD mode based on DT data

Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD
mode, make use of mode_rx field of dm_spi_slave_platdata to determine
whether to enable or disable QUAD mode. This is necessary to support
muliple SPI controllers where one of them may not support QUAD mode.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

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spi: cadence_qspi_apb: Support 32 bit AHB address

AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value

spi: cadence_qspi_apb: Support 32 bit AHB address

AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

mtd: cqspi: Simplify indirect read code

The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSP

mtd: cqspi: Simplify indirect read code

The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

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mtd: cqspi: Simplify indirect write code

The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in s

mtd: cqspi: Simplify indirect write code

The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.

This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

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