Lines Matching refs:reg
151 u32 cfg_tmp, reg = 0; in setup_serdes_volt() local
181 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
182 reg &= 0xFF9FFFFF; in setup_serdes_volt()
183 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
191 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
192 reg &= 0xFF9FFFFF; in setup_serdes_volt()
193 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
201 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
202 reg &= 0xFFFFFFBF; in setup_serdes_volt()
203 reg |= 0x10000000; in setup_serdes_volt()
204 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
207 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
208 reg &= 0xFFFFFF1F; in setup_serdes_volt()
209 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
217 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
218 reg &= 0xFFFFFFBF; in setup_serdes_volt()
219 reg |= 0x10000000; in setup_serdes_volt()
220 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
223 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
224 reg &= 0xFFFFFF1F; in setup_serdes_volt()
225 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
232 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
233 reg &= 0xF7FFFFFF; in setup_serdes_volt()
234 out_be32(&serdes1_base->srdstcalcr, reg); in setup_serdes_volt()
235 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
236 reg &= 0xF7FFFFFF; in setup_serdes_volt()
237 out_be32(&serdes1_base->srdsrcalcr, reg); in setup_serdes_volt()
241 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
242 reg &= 0xF7FFFFFF; in setup_serdes_volt()
243 out_be32(&serdes2_base->srdstcalcr, reg); in setup_serdes_volt()
244 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
245 reg &= 0xF7FFFFFF; in setup_serdes_volt()
246 out_be32(&serdes2_base->srdsrcalcr, reg); in setup_serdes_volt()
264 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
265 reg |= 0x00000020; in setup_serdes_volt()
266 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
269 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
270 reg |= 0x00000080; in setup_serdes_volt()
271 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
276 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
277 reg |= 0x08000000; in setup_serdes_volt()
278 out_be32(&serdes1_base->srdstcalcr, reg); in setup_serdes_volt()
279 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
280 reg |= 0x08000000; in setup_serdes_volt()
281 out_be32(&serdes1_base->srdsrcalcr, reg); in setup_serdes_volt()
290 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
291 reg |= 0x00000020; in setup_serdes_volt()
292 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
295 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
296 reg |= 0x00000080; in setup_serdes_volt()
297 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
302 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
303 reg |= 0x08000000; in setup_serdes_volt()
304 out_be32(&serdes2_base->srdstcalcr, reg); in setup_serdes_volt()
305 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
306 reg |= 0x08000000; in setup_serdes_volt()
307 out_be32(&serdes2_base->srdsrcalcr, reg); in setup_serdes_volt()
321 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()
322 if (!((reg >> 23) & 0x1)) { in setup_serdes_volt()
323 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
324 reg |= 0x20000000; in setup_serdes_volt()
325 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
328 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
329 reg &= 0xFFFFFFEF; in setup_serdes_volt()
330 reg |= 0x00000040; in setup_serdes_volt()
331 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
340 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()
341 if (!((reg >> 23) & 0x1)) { in setup_serdes_volt()
342 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
343 reg |= 0x20000000; in setup_serdes_volt()
344 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
347 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
348 reg &= 0xFFFFFFEF; in setup_serdes_volt()
349 reg |= 0x00000040; in setup_serdes_volt()
350 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
362 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
363 reg |= 0x00600000; in setup_serdes_volt()
364 out_be32(&serdes1_base->lane[i].gcr0, reg); in setup_serdes_volt()
372 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
373 reg |= 0x00600000; in setup_serdes_volt()
374 out_be32(&serdes2_base->lane[i].gcr0, reg); in setup_serdes_volt()
381 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()
382 if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { in setup_serdes_volt()
383 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
384 reg |= 0x40000000; in setup_serdes_volt()
385 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
392 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()
393 if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { in setup_serdes_volt()
394 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
395 reg |= 0x40000000; in setup_serdes_volt()
396 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()