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Searched refs:priv (Results 1 – 25 of 661) sorted by relevance

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/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c76 int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
103 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) in rockchip_combphy_is_ready() argument
105 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
117 static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) in rockchip_combphy_pcie_init() argument
122 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
123 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
125 dev_err(priv->dev, "failed to init phy for pcie\n"); in rockchip_combphy_pcie_init()
130 if (priv->cfg->force_det_out) { in rockchip_combphy_pcie_init()
131 val = readl(priv->mmio + (0x19 << 2)); in rockchip_combphy_pcie_init()
[all …]
H A Dphy-rockchip-snps-pcie3.c61 int (*phy_init)(struct rockchip_p3phy_priv *priv);
68 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) in rockchip_p3phy_rk3568_init() argument
74 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9, in rockchip_p3phy_rk3568_init()
78 if (priv->is_bifurcation) { in rockchip_p3phy_rk3568_init()
79 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON6, in rockchip_p3phy_rk3568_init()
81 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON1, in rockchip_p3phy_rk3568_init()
85 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4, in rockchip_p3phy_rk3568_init()
87 regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4, in rockchip_p3phy_rk3568_init()
89 reset_deassert(&priv->p30phy); in rockchip_p3phy_rk3568_init()
91 ret = regmap_read_poll_timeout(priv->phy_grf, in rockchip_p3phy_rk3568_init()
[all …]
/rk3399_rockchip-uboot/drivers/spi/
H A Ddesignware_spi.c117 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset) in dw_read() argument
119 return __raw_readl(priv->regs + offset); in dw_read()
122 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val) in dw_write() argument
124 __raw_writel(val, priv->regs + offset); in dw_write()
130 struct dw_spi_priv *priv = dev_get_priv(bus); in request_gpio_cs() local
134 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0); in request_gpio_cs()
143 if (dm_gpio_is_valid(&priv->cs_gpio)) { in request_gpio_cs()
144 dm_gpio_set_dir_flags(&priv->cs_gpio, in request_gpio_cs()
170 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) in spi_enable_chip() argument
172 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); in spi_enable_chip()
[all …]
H A Dpic32_spi.c83 static inline void pic32_spi_enable(struct pic32_spi_priv *priv) in pic32_spi_enable() argument
85 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); in pic32_spi_enable()
88 static inline void pic32_spi_disable(struct pic32_spi_priv *priv) in pic32_spi_disable() argument
90 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); in pic32_spi_disable()
93 static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv) in pic32_spi_rx_fifo_level() argument
95 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_rx_fifo_level()
100 static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv) in pic32_spi_tx_fifo_level() argument
102 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_tx_fifo_level()
108 static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes) in pic32_tx_max() argument
112 tx_left = (priv->tx_end - priv->tx) / n_bytes; in pic32_tx_max()
[all …]
H A Dzynq_qspi.c120 static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) in zynq_qspi_init_hw() argument
122 struct zynq_qspi_regs *regs = priv->regs; in zynq_qspi_init_hw()
162 struct zynq_qspi_priv *priv = dev_get_priv(bus); in zynq_qspi_probe() local
164 priv->regs = plat->regs; in zynq_qspi_probe()
165 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH; in zynq_qspi_probe()
168 zynq_qspi_init_hw(priv); in zynq_qspi_probe()
179 static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size) in zynq_qspi_read_data() argument
184 data, (unsigned)(priv->rx_buf), size); in zynq_qspi_read_data()
186 if (priv->rx_buf) { in zynq_qspi_read_data()
189 *((u8 *)priv->rx_buf) = data; in zynq_qspi_read_data()
[all …]
H A Domap3_spi.c123 static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val) in omap3_spi_write_chconf() argument
125 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
127 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
130 static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable) in omap3_spi_set_enable() argument
132 writel(enable, &priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
134 readl(&priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
137 static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len, in omap3_spi_write() argument
143 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write()
146 omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN); in omap3_spi_write()
149 chconf |= (priv->wordlen - 1) << 7; in omap3_spi_write()
[all …]
H A Dbcmstb_spi.c130 static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv) in bcmstb_spi_hw_set_parms() argument
132 writel(SPBR_MIN, &priv->regs->spcr0_lsb); in bcmstb_spi_hw_set_parms()
133 writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb); in bcmstb_spi_hw_set_parms()
163 struct bcmstb_spi_priv *priv = dev_get_priv(bus); in bcmstb_spi_probe() local
165 priv->regs = plat->base[HIF_MSPI]; in bcmstb_spi_probe()
166 priv->bspi = plat->base[BSPI]; in bcmstb_spi_probe()
167 priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2]; in bcmstb_spi_probe()
168 priv->cs_reg = plat->base[CS_REG]; in bcmstb_spi_probe()
169 priv->default_cs = 0; in bcmstb_spi_probe()
170 priv->curr_cs = -1; in bcmstb_spi_probe()
[all …]
H A Dfsl_qspi.c143 struct fsl_qspi_priv priv; member
170 static void qspi_set_lut(struct fsl_qspi_priv *priv) in qspi_set_lut() argument
172 struct fsl_qspi_regs *regs = priv->regs; in qspi_set_lut()
176 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE); in qspi_set_lut()
177 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK); in qspi_set_lut()
181 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) | in qspi_set_lut()
183 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); in qspi_set_lut()
184 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); in qspi_set_lut()
185 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); in qspi_set_lut()
190 qspi_write32(priv->flags, &regs->lut[lut_base], in qspi_set_lut()
[all …]
H A Dti_qspi.c117 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) in ti_spi_set_speed() argument
124 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; in ti_spi_set_speed()
133 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()
134 &priv->base->clk_ctrl); in ti_spi_set_speed()
136 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()
139 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv) in ti_qspi_cs_deactivate() argument
141 writel(priv->cmd | QSPI_INVAL, &priv->base->cmd); in ti_qspi_cs_deactivate()
143 readl(&priv->base->cmd); in ti_qspi_cs_deactivate()
146 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode) in __ti_qspi_set_mode() argument
148 priv->dc = 0; in __ti_qspi_set_mode()
[all …]
H A Dfsl_dspi.c104 struct fsl_dspi_priv priv; member
133 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt) in dspi_halt() argument
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in dspi_halt()
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in dspi_halt()
147 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val) in fsl_dspi_init_mcr() argument
150 dspi_halt(priv, 1); in fsl_dspi_init_mcr()
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); in fsl_dspi_init_mcr()
155 dspi_halt(priv, 0); in fsl_dspi_init_mcr()
157 priv->mcr_val = cfg_val; in fsl_dspi_init_mcr()
160 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv, in fsl_dspi_cfg_cs_active_state() argument
[all …]
H A Dstm32_qspi.c180 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv) in _stm32_qspi_disable() argument
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_disable()
185 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv) in _stm32_qspi_enable() argument
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_enable()
190 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_not_busy() argument
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) in _stm32_qspi_wait_for_not_busy()
196 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_complete() argument
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) in _stm32_qspi_wait_for_complete()
202 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) in _stm32_qspi_wait_for_ftf() argument
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) in _stm32_qspi_wait_for_ftf()
[all …]
/rk3399_rockchip-uboot/drivers/video/exynos/
H A Dexynos_fb.c103 static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled) in exynos_fimd_set_dualrgb() argument
105 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dualrgb()
113 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
120 static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv, in exynos_fimd_set_dp_clkcon() argument
123 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_dp_clkcon()
132 static void exynos_fimd_set_par(struct exynos_fb_priv *priv, in exynos_fimd_set_par() argument
135 struct exynos_fb *reg = priv->reg; in exynos_fimd_set_par()
155 switch (priv->vl_bpix) { in exynos_fimd_set_par()
172 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | in exynos_fimd_set_par()
173 EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) | in exynos_fimd_set_par()
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Dxilinx_gpio.c51 struct xilinx_gpio_priv *priv = NULL; in gpio_get_controller() local
54 priv = list_entry(entry, struct xilinx_gpio_priv, list); in gpio_get_controller()
55 if (gpio >= priv->gpio_min && gpio <= priv->gpio_max) { in gpio_get_controller()
57 (u32)priv->regs, priv->gpio_min, priv->gpio_max); in gpio_get_controller()
58 return priv; in gpio_get_controller()
69 struct xilinx_gpio_priv *priv; in get_name() local
73 priv = gpio_get_controller(gpio); in get_name()
74 if (priv) { in get_name()
75 gpio_priv = gpio - priv->gpio_min; in get_name()
77 return *priv->gpio_name[gpio_priv].name ? in get_name()
[all …]
/rk3399_rockchip-uboot/arch/sandbox/cpu/
H A Deth-raw-os.c30 struct eth_sandbox_raw_priv *priv) in _raw_packet_start() argument
38 priv->device = malloc(sizeof(struct sockaddr_ll)); in _raw_packet_start()
39 if (priv->device == NULL) in _raw_packet_start()
41 device = priv->device; in _raw_packet_start()
49 priv->sd = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL)); in _raw_packet_start()
50 if (priv->sd < 0) { in _raw_packet_start()
56 ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname, in _raw_packet_start()
65 flags = fcntl(priv->sd, F_GETFL, 0); in _raw_packet_start()
66 fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); in _raw_packet_start()
71 ret = setsockopt(priv->sd, SOL_PACKET, PACKET_ADD_MEMBERSHIP, in _raw_packet_start()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c124 struct rk3506_clk_priv *priv; in soc_clk_dump() local
140 priv = dev_get_priv(cru_dev); in soc_clk_dump()
141 sel = (readl(&priv->cru->clksel_con[15]) & in soc_clk_dump()
148 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
149 priv->armclk_enter_hz / 1000, in soc_clk_dump()
150 priv->armclk_init_hz / 1000, in soc_clk_dump()
151 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
152 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
185 static int rk3506_armclk_get_rate(struct rk3506_clk_priv *priv) in rk3506_armclk_get_rate() argument
187 struct rk3506_cru *cru = priv->cru; in rk3506_armclk_get_rate()
[all …]
H A Dclk_rv1126.c97 static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,
151 static ulong rv1126_gpll_get_pmuclk(struct rv1126_pmuclk_priv *priv) in rv1126_gpll_get_pmuclk() argument
154 priv->pmucru, GPLL); in rv1126_gpll_get_pmuclk()
160 struct rv1126_clk_priv *priv; in rv1126_gpll_set_pmuclk() local
170 priv = dev_get_priv(cru_dev); in rv1126_gpll_set_pmuclk()
172 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { in rv1126_gpll_set_pmuclk()
179 static ulong rv1126_rtc32k_get_pmuclk(struct rv1126_pmuclk_priv *priv) in rv1126_rtc32k_get_pmuclk() argument
181 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_get_pmuclk()
194 static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv, in rv1126_rtc32k_set_pmuclk() argument
197 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_set_pmuclk()
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dethoc.c202 static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset) in ethoc_reg() argument
204 return priv->iobase + offset; in ethoc_reg()
207 static inline u32 ethoc_read(struct ethoc *priv, size_t offset) in ethoc_read() argument
209 return readl(ethoc_reg(priv, offset)); in ethoc_read()
212 static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data) in ethoc_write() argument
214 writel(data, ethoc_reg(priv, offset)); in ethoc_write()
217 static inline void ethoc_read_bd(struct ethoc *priv, int index, in ethoc_read_bd() argument
221 bd->stat = ethoc_read(priv, offset + 0); in ethoc_read_bd()
222 bd->addr = ethoc_read(priv, offset + 4); in ethoc_read_bd()
225 static inline void ethoc_write_bd(struct ethoc *priv, int index, in ethoc_write_bd() argument
[all …]
H A Dcpsw.c248 #define for_active_slave(slave, priv) \ argument
249 slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
250 #define for_each_slave(slave, priv) \ argument
251 for (slave = (priv)->slaves; slave != (priv)->slaves + \
252 (priv)->data.slaves; slave++)
338 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) in cpsw_ale_read() argument
342 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); in cpsw_ale_read()
345 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_read()
350 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) in cpsw_ale_write() argument
355 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_write()
[all …]
H A Dtsec.c70 static void tsec_configure_serdes(struct tsec_private *priv) in tsec_configure_serdes() argument
76 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
78 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
80 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), in tsec_configure_serdes()
110 struct tsec_private *priv = (struct tsec_private *)dev->priv; in tsec_mcast_addr() local
111 struct tsec __iomem *regs = priv->regs; in tsec_mcast_addr()
181 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) in adjust_link() argument
183 struct tsec __iomem *regs = priv->regs; in adjust_link()
241 struct tsec_private *priv = (struct tsec_private *)dev->priv; in tsec_send() local
242 struct tsec __iomem *regs = priv->regs; in tsec_send()
[all …]
H A Dep93xx_eth.c29 #define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
44 struct ep93xx_priv *priv = GET_PRIV(dev); in dump_dev() local
48 printf(" rx_dq.base %p\n", priv->rx_dq.base); in dump_dev()
49 printf(" rx_dq.current %p\n", priv->rx_dq.current); in dump_dev()
50 printf(" rx_dq.end %p\n", priv->rx_dq.end); in dump_dev()
51 printf(" rx_sq.base %p\n", priv->rx_sq.base); in dump_dev()
52 printf(" rx_sq.current %p\n", priv->rx_sq.current); in dump_dev()
53 printf(" rx_sq.end %p\n", priv->rx_sq.end); in dump_dev()
58 printf(" tx_dq.base %p\n", priv->tx_dq.base); in dump_dev()
59 printf(" tx_dq.current %p\n", priv->tx_dq.current); in dump_dev()
[all …]
H A Dsun8i_emac.c148 struct udevice *dev = bus->priv; in sun8i_mdio_read()
149 struct emac_eth_dev *priv = dev_get_priv(dev); in sun8i_mdio_read() local
166 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); in sun8i_mdio_read()
170 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) in sun8i_mdio_read()
171 return readl(priv->mac_reg + EMAC_MII_DATA); in sun8i_mdio_read()
181 struct udevice *dev = bus->priv; in sun8i_mdio_write()
182 struct emac_eth_dev *priv = dev_get_priv(dev); in sun8i_mdio_write() local
198 writel(val, priv->mac_reg + EMAC_MII_DATA); in sun8i_mdio_write()
199 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); in sun8i_mdio_write()
203 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & in sun8i_mdio_write()
[all …]
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Ddwc3-meson-g12a.c125 static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv, in dwc3_meson_g12a_usb2_set_mode() argument
132 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), in dwc3_meson_g12a_usb2_set_mode()
138 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), in dwc3_meson_g12a_usb2_set_mode()
144 static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv) in dwc3_meson_g12a_usb2_init() argument
148 if (priv->otg_mode == USB_DR_MODE_PERIPHERAL) in dwc3_meson_g12a_usb2_init()
149 priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL; in dwc3_meson_g12a_usb2_init()
151 priv->otg_phy_mode = USB_DR_MODE_HOST; in dwc3_meson_g12a_usb2_init()
154 if (!priv->phys[i].dev) in dwc3_meson_g12a_usb2_init()
157 regmap_update_bits(priv->regmap, U2P_R0 + (U2P_REG_SIZE * i), in dwc3_meson_g12a_usb2_init()
162 regmap_update_bits(priv->regmap, in dwc3_meson_g12a_usb2_init()
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Dpwm_backlight.c31 struct pwm_backlight_priv *priv = dev_get_priv(dev); in pwm_backlight_enable() local
36 if (priv->reg) { in pwm_backlight_enable()
37 plat = dev_get_uclass_platdata(priv->reg); in pwm_backlight_enable()
39 dev->name, priv->reg->name, plat->name); in pwm_backlight_enable()
40 ret = regulator_set_enable(priv->reg, true); in pwm_backlight_enable()
49 ret = pwm_set_invert(priv->pwm, priv->channel, priv->polarity); in pwm_backlight_enable()
55 duty_cycle = priv->period_ns * (priv->default_level - priv->min_level) / in pwm_backlight_enable()
56 (priv->max_level - priv->min_level + 1); in pwm_backlight_enable()
57 ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, in pwm_backlight_enable()
61 ret = pwm_set_enable(priv->pwm, priv->channel, true); in pwm_backlight_enable()
[all …]
H A Dvidconsole-uclass.c62 struct vidconsole_priv *priv = dev_get_uclass_priv(dev); in vidconsole_back() local
72 priv->xcur_frac -= VID_TO_POS(priv->x_charsize); in vidconsole_back()
73 if (priv->xcur_frac < priv->xstart_frac) { in vidconsole_back()
74 priv->xcur_frac = (priv->cols - 1) * in vidconsole_back()
75 VID_TO_POS(priv->x_charsize); in vidconsole_back()
76 priv->ycur -= priv->y_charsize; in vidconsole_back()
77 if (priv->ycur < 0) in vidconsole_back()
78 priv->ycur = 0; in vidconsole_back()
88 struct vidconsole_priv *priv = dev_get_uclass_priv(dev); in vidconsole_newline() local
94 priv->xcur_frac = priv->xstart_frac; in vidconsole_newline()
[all …]
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dohci-sunxi.c39 struct ohci_sunxi_priv *priv = dev_get_priv(dev); in ohci_usb_probe() local
43 priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in ohci_usb_probe()
44 if (IS_ERR(priv->ccm)) in ohci_usb_probe()
45 return PTR_ERR(priv->ccm); in ohci_usb_probe()
53 priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; in ohci_usb_probe()
57 priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; in ohci_usb_probe()
58 priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; in ohci_usb_probe()
59 priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; in ohci_usb_probe()
60 extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; in ohci_usb_probe()
61 priv->usb_gate_mask <<= priv->phy_index; in ohci_usb_probe()
[all …]

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